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| 型号： | 440GRX |
| 厂商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440GRx Embedded Processor |
| 中文描述： | 嵌入式处理器的PowerPC 440GRx |
| 文件页数： | 51/88页 |
| 文件大小： | 603K |
| 代理商： | 440GRX |
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440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
55
Preliminary Data Sheet
Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin
has multiple signal names assigned to distinguish different modes of operation, all of the names are shown.
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 86). Note that
these are not multiplexed pins since the function of the pins is not programmable.
Reserved Pins
The pins classified as Reserved are not functional and must be connected as shown in Table 8.
Unused I/Os
Termination of unused receivers is generally required; however, there are some exceptions that reduce or
eliminate the need for termination.
Signals Multiplexed with GPIO:
By default after reset, signals shared with GPIO pins are configured as GPIO receivers. Termination however,
is not needed if the GPIO during initialization are configured as outputs. To configure as drivers, set and clear
the appropriate bits in the GPIOx_ODR, GPIOx_TCR and GPIOx_OR registers as described in the GPIO
chapter of the user’s manual.
PCI:
When the PCI bridge is unused, configure the PCI controller to park on the bus by pulling the PCIReq0[Gnt]
signal low. Parking forces the PLB3 to PCI bridge to actively drive PCIAD31:0 and PCIC3:0[BE3:0]. The
remaining PCI control signals must be terminated as follows:
– Disable the internal PCI arbiter and enable PCI sychronous mode (See IIC Boot Strap Chapter in the
User’s Manual).
Note:
Synchronous mode is not supported when operating the PCI bus. This mode should only be used for
terminating an unused PCI interface).
– Individually connect PCISErr, PCIPErr, PCITRDY, and PCISTOP through 3kΩ resistors to +3.3V.
– Individually connect PCIReq1:5 through 3kΩ resistors to +3.3V.
– Connect PCIReq0[Gnt] through 1kΩ resistor to GND.
DDR:
– In 32 bit mode, termination is not needed on the upper data, strobe and mask signals when the DDR I/O
and DDR controller are configured for 32 bit mode, SDR0_DDRCFG[64B32B]=0 and
DDR0_14[REDUC=1.
– Termination of unused ECC signals (ECC0:7, DM8, DQS8) is not needed.
Table 8. Reserved Pin Connections
Pin
Connection
A05
GND
J01
Open
J02
Open
L03
OVDD
N02
GND
N03
GND
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 440GS001NF1934-4 | 功能描述:环形MIL规格后盖 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440GS001NF2535-4 | 功能描述:环形MIL规格后盖 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440GS031B2912-4 | 制造商:Glenair Inc 功能描述:Shrink Boot Adapters 180° 29 Shell Size Olive Drab Cadmium Aluminum Direct 制造商:Glenair 功能描述:Shrink Boot Adapters 180° 29 Shell Size Olive Drab Cadmium Aluminum Direct |
| 440GS031B3314-4 | 制造商:Glenair Inc 功能描述:Shrink Boot Adapters 180° 33 Shell Size Olive Drab Cadmium Aluminum Direct 制造商:Glenair 功能描述:Shrink Boot Adapters 180° 33 Shell Size Olive Drab Cadmium Aluminum Direct |
| 440GS031NF1102-3BT | 功能描述:环形MIL规格后盖 BND/SHRNK BOOT ADPTR DC STRT BAND BOOT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
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