参数资料
型号: 440GRX
厂商: Applied Micro Circuits Corp.
英文描述: PowerPC 440GRx Embedded Processor
中文描述: 嵌入式处理器的PowerPC 440GRx
文件页数: 53/88页
文件大小: 603K
代理商: 440GRX
440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
57
Preliminary Data Sheet
DDR2/1 SDRAM Interface
BA0:2
Bank Address supporting up to eight internal banks.
O
2.5V (1.8V)
SDRAM-DDR
BankSel0:1
Selects up to two external DDR SDRAM banks.
O
2.5V (1.8V)
SDRAM-DDR
CAS
Column Address Strobe.
O
2.5V (1.8V)
SDRAM-DDR
ClkEn
Clock Enable.
O
2.5V (1.8V)
SDRAM-DDR
DM0:7
DM8
Memory write data byte lane masks. DM8 is the byte lane
mask for the ECC byte lane.
O
2.5V (1.8V)
SDRAM-DDR
DQS0:7
DQS8
Byte lane data strobe.
Byte lane data strobe for ECC.
I/O
2.5V (1.8V)
SDRAM-DDR
ECC0:7
ECC check bits 0:7.
I/O
2.5V (1.8V)
SDRAM-DDR
MemAddr00:13
Memory address bus.
O
2.5V (1.8V)
SDRAM-DDR
MemData00:63
Memory data bus (MemData32:63 available for DDR2 only).
I/O
2.5V (1.8V)
SDRAM-DDR
MemClkOut
Subsystem clock.
O
2.5V (1.8V)
SDRAM-DDR
Diff driver
MemODT0:1
DDR2 On-die termination enable (not used with DDR1).
O
2.5V (1.8V)
SDRAM-DDR
RAS
Row Address Strobe.
O
2.5V (1.8V)
SDRAM-DDR
WE
Write Enable.
O
2.5V (1.8V)
SDRAM-DDR
SVREF1A:B
DDR SDRAM reference voltage 1 input.
I
Volt ref receiver
(1.25V or 0.9V)
SVREF2A:B
DDR SDRAM reference voltage 2 input.
I
Volt ref driver
(1.25V or 0.9V)
Table 9. Signal Functional Description (Sheet 2 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to OV
DD (EOVDD for Ethernet)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to OV
DD (EOVDD for Ethernet)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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