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| 型号： | 440GRX |
| 厂商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440GRx Embedded Processor |
| 中文描述： | 嵌入式处理器的PowerPC 440GRx |
| 文件页数： | 57/88页 |
| 文件大小： | 603K |
| 代理商： | 440GRX |
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440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
60
AMCC Proprietary
Revision 1.08 – October 15, 2007
External Master Peripheral Interface
BusReq
Bus Request. Used when the PPC440GRx needs to regain
control of peripheral interface from an external master.
O3.3V LVTTL
ExtAck
External Acknowledgement. Used by the PPC440GRx to
indicate that a data transfer occurred.
O3.3V LVTTL
ExtReq
External Request. Used by an external master to indicate it is
prepared to transfer data.
I3.3V LVTTL
1
ExtReset
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
Note: The state of signals or clocks cannot be guaranteed
until the ExtReset signal has been de-asserted.
O3.3V LVTTL
HoldAck
Hold Acknowledge. Used by the PPC440GRx to transfer
ownership of peripheral bus to an external master.
O3.3V LVTTL
HoldReq
Hold Request. Used by an external master to request
ownership of the peripheral bus.
I3.3V LVTTL
HoldPri
Hold Primary. Used by an external master to indicate the
priority of a given external master tenure.
I
3.3V LVTTL
w/pull-up
PerClk
Peripheral Clock. Used by an external master and by
synchronous peripheral slaves.
O3.3V LVTTL
1
UART Peripheral Interface
The UART interface can be configured as follows:
1. One 8-pin, where n = 0
2. Two 4-pin, where n = 0 & 1
3. One 4-pin, where n = 0 and two 2-pin, where n = 1 & 2
4. Four 2-pin, where n = 0 & 1 & 2 & 3
UARTSerClk
The SerClk input provides an alternative to the internally
generated serial clock. It is used in cases where the allowable
internally generated clock rates are not satisfactory.
I
3.3V LVTTL
1, 4
UARTn_Rx
Receive data.
I
3.3V LVTTL
Rcvr
1, 4
UARTn_Tx
Transmit data.
O
3.3V LVTTL
UARTn_DCD
Data Carrier Detect.
I
3.3V LVTTL
1, 6
UARTn_DSR
Data Set Ready.
I
3.3V LVTTL
1, 6
UARTn_CTS
Clear To Send.
I
3.3V LVTTL
1, 6
UARTn_DTR
Data Terminal Ready.
O
3.3V LVTTL
1
UARTn_RTS
Request To Send.
O
3.3V LVTTL
1
UARTn_RI
Ring Indicator.
I
3.3V LVTTL
1
IIC Peripheral Interface
IIC0SClk
IIC0 Serial Clock.
I/O
3.3V LVTTL
1, 2
IIC0SData
IIC0 Serial Data.
I/O
3.3V LVTTL
1, 2
IIC1SClk
IIC1 Serial Clock.
I/O
3.3V LVTTL
1
IIC1SData
IIC1 Serial Data.
I/O
3.3V LVTTL
Table 9. Signal Functional Description (Sheet 5 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to OV
DD (EOVDD for Ethernet)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to OV
DD (EOVDD for Ethernet)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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相关代理商/技术参数 |
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| 440GS001NF1934-4 | 功能描述:环形MIL规格后盖 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440GS001NF2535-4 | 功能描述:环形MIL规格后盖 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440GS031B2912-4 | 制造商:Glenair Inc 功能描述:Shrink Boot Adapters 180° 29 Shell Size Olive Drab Cadmium Aluminum Direct 制造商:Glenair 功能描述:Shrink Boot Adapters 180° 29 Shell Size Olive Drab Cadmium Aluminum Direct |
| 440GS031B3314-4 | 制造商:Glenair Inc 功能描述:Shrink Boot Adapters 180° 33 Shell Size Olive Drab Cadmium Aluminum Direct 制造商:Glenair 功能描述:Shrink Boot Adapters 180° 33 Shell Size Olive Drab Cadmium Aluminum Direct |
| 440GS031NF1102-3BT | 功能描述:环形MIL规格后盖 BND/SHRNK BOOT ADPTR DC STRT BAND BOOT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
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