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参数资料
| 型号： | 5962-9169101MXA |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 封装： | CERDIP-28 |
| 文件页数： | 11/48页 |
| 文件大小： | 647K |
| 代理商： | 5962-9169101MXA |
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calibration cycle on th e CS5102A takes
2,882,040 master clock cycles to complete (ap-
proximately 1.8 seconds with a 1.6 MHz master
clock). The CS5101A’s and CS5102A’s STBY
output remains low throughout the calibration se-
quence, and a rising transition indicates the
device is ready for normal operation. While cali-
brating, the CS5101A and CS5102A will ignore
changes on the HOLD input.
To perform the reset function, a simple power-on
reset circuit can be built using a resistor and ca-
pacitor as shown in Figure 8. The resistor should
be less than or equal to 10 k
. The system power
supplies, voltage reference, and clock should all
be established prior RST rising.
Single-Channel Operation
The CS5101A and CS5102A can alternatively be
used to sample one channel by tying the CH1/2
input high or low. The unused AIN pin should be
tied to the analog input signal or to AGND. (If
operating in free run mode, AIN1 and AIN2 must
VA+
VD+
10
+5VA
+
4.7
F
0.1
F
+
1
F
0.1
F
23
1
10
++
-5VA
4.7
F
0.1
F1 F
0.1
F
0.1
F
21
VA-
VD-
REFBUF
25
7
CLKIN
XOUT
6
DGND
SLEEP
STBY
TRK1
TRK2
SSH/SDL
SDATA
RST
CH1/2
SCLK
HOLD
10 M
3
4
EXT
CLOCK
C2 = C1
10
28
5
8
9
11
15
2
13
14
12
Data
Interface
Control
Logic
CRS/FIN
16
17
27
18
26
CODE
SCKMOD
OUTMOD
BP/UP
VD+
Mode Control
AIN1
AIN2
19
24
50
1 nF
50
1 nF
Analog
Sources
VREF
AGND
20
22
Voltage Reference
*
* For best dynamic
S/(N+D) performance.
NPO
Unused Logic inputs should
be tied to VD+ or DGND.
C1
CS5101A
OR
CS5102A
XTAL
XTAL & C1 Table
CS5101A
FRN
CS5102A
FRN
XTAL
8.0 MHz
8.192 MHz
1.6 MHz
C1, C2
10 pF
30 pF
2.0 MHz
1.6 MHz
or
TST
PDT, RBT,
SSC
PDT, RBT,
SSC
Figure 7. CS5101A/CS5102A System Connection Diagram
CS5101A CS5102A
DS45F2
19
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