- 您现在的位置：买卖IC网 > PDF目录67334 > 5962-9169101MXA (CRYSTAL SEMICONDUCTOR CORP) 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 PDF资料下载
参数资料
| 型号： | 5962-9169101MXA |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 封装： | CERDIP-28 |
| 文件页数： | 8/48页 |
| 文件大小： | 647K |
| 代理商： | 5962-9169101MXA |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
Output Mode Control
The CS5101A and CS5102A can be configured
in three different output modes, as well as an in-
ternal, synchronous loop-back mode. This allows
great flexibility for design into a wide variety of
systems. The operating mode is selected by set-
ting the states of the SCKMOD and OUTMOD
pins. In all modes, data is output on SDATA,
starting with the MSB. Each subsequent data bit
is updated on the falling edge of SCLK.
When SCKMOD is high, SCLK is an input, al-
lowing the data to be clocked out with an
external serial clock at rates up to 5 MHz. Addi-
tional clock edges after #16 will clock out logic
’1’s on SDATA. Tying SCKMOD low reconfig-
ures SCLK as an output, and the converter clocks
out each bit as it’s determined during the conver-
sion process, at a rate of 1/4 the master clock
speed. Table 2 shows an overview of the different
states of SCKMOD and OUTMOD, and the cor-
responding output modes.
Pipelined Data Transmission (PDT)
PDT mode is selected by tying both SCKMOD
and OUTMOD high. In PDT mode, the SCLK
pin is an input. Data is registered during conver-
sion, and output during the following conversion
cycle. HOLD must be brought low, initiating an-
other conversion, before data from the previous
conversion is available on SDATA. If all the data
has not been clocked out before the next falling
edge of HOLD, the old data will be lost
(Figure 3).
Figure 3. Pipelined Data Transmission Mode (PDT)
CLKIN (i)
HOLD (i)
Internal
Status
SCLK (i)
SDATA (o)
CH1/2 (i)
D15
D14
D1 D0 (Ch. 1)
TRK1 (o)
TRK2 (o)
SSH/SDL (o)
Converting Ch. 2
D15
D14
D1
D0 (Ch. 2)
Converting Ch. 1
D15
68
72
76
0
4
8
6468
7276
4
8
64
60
00
Tracking Ch. 1
Tracking Ch. 2
SCLK
Input
Output
Input
Output
OUTMOD
0
1
0
1
SCKMOD
0
1
0
1
MODE
PDT
RBT
SSC
FRN
Input
Output
CH1/2
X
Input
HOLD
Table 2. Serial Output Modes
CS5101A CS5102A
16
DS45F2
相关PDF资料 |
PDF描述 |
|---|---|
| 5962-9169102M3A | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 5962-9169202MXA | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 5962-9169102MXA | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 5962-9169201M3A | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 5962-9169202M3A | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 5962-9169301M2A | 制造商:Texas Instruments 功能描述:-LIFETIME BUYS TIL 03/03 |
| 5962-9169701MMA | 制造商:e2v Aerospace & Defense 功能描述:SMD MKD 87C51RC-16 PHI-JLCC |
| 5962-9169701MUA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| 5962-9169702MUA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 5962-9172201MEA | 制造商:e2v 功能描述:Counter Single 4-Bit Binary UP 16-Pin CDIP 制造商:e2v technologies 功能描述:Counter Single 4-Bit Binary UP 16-Pin CDIP |
发布紧急采购，3分钟左右您将得到回复。