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参数资料
| 型号： | 5962-9169101MXA |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 封装： | CERDIP-28 |
| 文件页数： | 15/48页 |
| 文件大小： | 647K |
| 代理商： | 5962-9169101MXA |
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Fine-charge settling is specified as a maximum of
1.125
s (CS5101A) or 5.625 s (CS5102A) for
an analog source impedance of less than 50
. In
addition, the comparator requires a source imped-
ance of less than 400
around 2 MHz for
stability. The source impedance can be effectively
reduced at high frequencies by adding capaci-
tance from AIN to ground (typically 200 pF).
However, high dc source resistances will increase
the input’s RC time constant and extend the nec-
essary acquisition time. For more information on
input amplifiers, consult the application note:
Buffer Amplifiers for the CS501X Series of A/D
Converters.
SLEEP Mode Operation
The CS5101A and CS5102A include a SLEEP
pin. When SLEEP is active (low) each device
will dissipate very low power to retain its calibra-
tion memory when the device is not sampling. It
does not require calibration after SLEEP is made
inactive (high). When coming out of SLEEP,
sampling can begin as soon as the oscillator starts
(time will depend on the particular oscillator
components) and the REFBUF capacitor is
charged (which takes about 3 ms for the
CS5101A, 50 ms for the CS5102A). To achieve
minimum start-up time, use an external clock and
leave the voltage reference powered-up. Connect
a resistor (2 k
) between pins 20 and 21 to keep
the REFBUF capacitor charged. Conversion can
then begin as soon as the A/D circuitry has stabi-
lized and performed a track cycle.
To retain calibration memory while SLEEP is ac-
tive (low) VA+ and VD+ must be maintained at
greater than 2.0V. VA- and VD- can be allowed
to go to 0 volts. The voltages into VA- and VD-
cannot just be "shut-off" as these pins cannot be
allowed to float to potentials greater than
AGND/DGND. If the supply voltages to VA- and
VD- are removed, use a transistor switch to short
these to the power supply ground while in
SLEEP mode.
Grounding and Power Supply Decoupling
The CS5101A and CS5102A use the analog
ground connection, AGND, only as a reference
voltage. No dc power currents flow through the
AGND connection, and it is completely inde-
pendent of DGND. However, any noise riding on
the AGND input relative to the system’s analog
ground will induce conversion errors. Therefore,
both the analog input and reference voltage
should be referred to the AGND pin, which
should be used as the entire system’s analog
ground reference.
The digital and analog supplies are isolated
within the CS5101A and CS5102A and are
pinned out separately to minimize coupling be-
tween the analog and digital sections of the chip.
All four supplies should be decoupled to their re-
spective grounds using 0.1
F ceramic capacitors.
If significant low-frequency noise is present on
the supplies, tantalum capacitors are recom-
mended in parallel with the 0.1
F capacitors.
The positive digital power supply of the
CS5101A and CS5102A must never exceed the
positive analog supply by more than a diode drop
or the CS5101A and CS5102A could experience
permanent damage. If the two supplies are de-
rived from separate sources, care must be taken
that the analog supply comes up first at power-
up. The system connection diagram (Figure 7)
shows a decoupling scheme which allows the
CS5101A and CS5102A to be powered from a
single set of
± 5V rails. The positive digital sup-
ply is derived from the analog supply through a
10
resistor to avoid the analog supply dropping
below the digital supply. If this scheme is util-
ized, care must be taken to insure that any digital
load currents (which flow through the 10
resis-
tors) do not cause the magnitude of digital
supplies to drop below the analog supplies by
more than 0.5 volts. Digital supplies must always
remain above the minimum specification.
CS5101A CS5102A
22
DS45F2
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