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参数资料
| 型号： | 5962-9319501MYA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封装： | EL44A |
| 文件页数： | 15/43页 |
| 文件大小： | 991K |
| 代理商： | 5962-9319501MYA |
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Application Information
1.0 Functional Description
The LM12454 and LM12(H)458 are multi-functional Data Ac-
quisition
Systems
that
include
a
fully
differential
12-bit-plus-sign self-calibrating analog-to-digital converter
(ADC) with a two’s-complement output format, an 8-channel
(LM12(H)458) or a 4-channel (LM12454) analog multiplexer,
an internal 2.5V reference, a first-in-first-out (FIFO) register
that can store 32 conversion results, and an Instruction RAM
that can store as many as eight instructions to be sequen-
tially executed. The LM12454 also has a differential multi-
plexer output and a differential S/H input. All of this circuitry
operates on only a single +5V power supply.
The LM12(H)454/8 have three modes of operation:
12-bit + sign with correction
8-bit + sign without correction
8-bit + sign comparison mode (“watchdog” mode)
The fully differential 12-bit-plus-sign ADC uses a charge re-
distribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC. The DAC is used
by a successive approximation register to generate interme-
diate voltages between the voltages applied to V
REF and
V
REF+. These intermediate voltages are compared against
the sampled analog input voltage as each bit is generated.
The number of intermediate voltages and comparisons
equals the ADC’s resolution. The correction of each bit’s ac-
curacy is accomplished by calibrating the capacitor ladder
used in the ADC.
Two different calibration modes are available; one compen-
sates for offset voltage, or zero error, while the other corrects
both offset error and the ADC’s linearity error.
When correcting offset only, the offset error is measured
once and a correction coefficient is created. During the full
calibration, the offset error is measured eight times, aver-
aged, and a correction coefficient is created. After comple-
tion of either calibration mode, the offset correction coeffi-
cient is stored in an internal offset correction register.
The LM12(H)454/8’s overall linearity correction is achieved
by correcting the internal DAC’s capacitor mismatch. Each
capacitor is compared eight times against all remaining
smaller value capacitors and any errors are averaged. A cor-
rection coefficient is then created and stored in one of the
thirteen internal linearity correction registers. An internal
state machine, using patterns stored in an internal 16 x 8-bit
ROM, executes each calibration algorithm.
Once calibrated, an internal arithmetic logic unit (ALU) uses
the offset correction coefficient and the 13 linearity correction
coefficients to reduce the conversion’s offset error and lin-
earity error, in the background, during the 12-bit + sign con-
version. The 8-bit + sign conversion and comparison modes
use only the offset coefficient. The 8-bit + sign mode per-
forms a conversion in less than half the time used by the
12-bit + sign conversion mode.
The LM12(H)454/8’s “watchdog” mode is used to monitor a
single-ended
or
differential
signal’s
amplitude.
Each
sampled signal has two limits. An interrupt can be generated
if the input signal is above or below either of the two limits.
This allows interrupts to be generated when analog voltage
inputs are “inside the window” or, alternatively, “outside the
window”. After a “watchdog” mode interrupt, the processor
can then request a conversion on the input signal and read
the signal’s magnitude.
The analog input multiplexer can be configured for any com-
bination of single-ended or fully differential operation. Each
input is referenced to ground when a multiplexer channel op-
erates in the single-ended mode. Fully differential analog in-
put channels are formed by pairing any two channels to-
gether.
The LM12454’s multiplexer outputs and S/H inputs (MUX-
OUT+, MUXOUT and S/H IN+, S/H IN) provide the option
for additional analog signal processing. Fixed-gain amplifi-
ers, programmable-gain amplifiers, filters, and other pro-
cessing circuits can operate on the signal applied to the se-
lected multiplexer channel(s). If external processing is not
used, connect MUXOUT+ to S/H IN+ and MUXOUT to
S/H IN.
The LM12(H)454/8’s internal S/H is designed to operate at
its minimum acquisition time (1.13 s, 12 bits) when the
source impedance, R
S,is ≤ 60 (fCLK ≤ 8 MHz). When 60
< R
S ≤ 4.17 k, the internal S/H’s acquisition time can be in-
creased to a maximum of 4.88 s (12 bits, f
CLK = 8 MHz).
See Section 2.1 (Instruction RAM “00”) Bits 12–15 for more
information.
An internal 2.5V bandgap reference output is available at pin
44. This voltage can be used as the ADC reference for ratio-
metric conversion or as a virtual ground for front-end analog
conditioning circuits. The V
REFOUT pin should be bypassed
to ground with a 100 F capacitor.
Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conver-
sions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at any
time, interrogate the FIFO and retrieve its contents. It can
also wait for the LM12(H)454/8 to issue an interrupt when
the FIFO is full or after any number (
≤32) of conversions
have been stored.
Conversion sequencing, internal timer interval, multiplexer
configuration, and many other operations are programmed
and set in the Instruction RAM.
A diagnostic mode is available that allows verification of the
LM12(H)458’s operation. The diagnostic mode is disabled in
the LM12454. This mode internally connects the voltages
present at the V
REFOUT,VREF+,VREF, and GND pins to the
internal V
IN+ and VIN S/H inputs. This mode is activated by
setting the Diagnostic bit (Bit 11) in the Configuration register
to a “1”. More information concerning this mode of operation
can be found in Section 2.2.
2.0 Internal User-Programmable
Registers
INSTRUCTION RAM
The instruction RAM holds up to eight sequentially execut-
able instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction’s address
and the 2-bit “RAM pointer” in the Configuration register. The
eight instructions are located at addresses 0000 through
0111 (A4–A1, BW = 0) when using a 16-bit wide data bus or
at addresses 00000 through 01111 (A4–A0, BW = 1) when
using an 8-bit wide data bus. They can be accessed and pro-
grammed in random order.
www.national.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 5962-9319801HXA | 功能描述:模数转换器 - ADC Analog to Digital Converter RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| 5962-9319801HXC | 功能描述:模数转换器 - ADC Analog to Digital Converter RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| 5962-9319803HXA | 功能描述:模数转换器 - ADC Analog to Digital Converter RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| 5962-9319803HXC | 功能描述:模数转换器 - ADC Analog to Digital Converter RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| 59629319901MXA | 制造商:TI 功能描述:SNJ54ABT16240WD |
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