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参数资料
型号： 5962-9319501MYA
厂商： NATIONAL SEMICONDUCTOR CORP
元件分类： 模拟信号调理
英文描述： SPECIALTY ANALOG CIRCUIT, PQCC44
封装： EL44A
文件页数： 42/43页
文件大小： 991K
代理商： 5962-9319501MYA
Internal Reference Characteristics (Notes 6, 7, 19) (Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for V
A+ = VD+ = 5V unless otherwise specified.
Boldface limits apply for T
A = TJ = TMIN to TMAX; all other limits TA = TJ = 25C.
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
t
SU
Internal Reference Start-Up Time
V
A+ = VD+ = 0V → 5V
10
ms
C
L = 100 F
Digital Characteristics (Notes 6, 7, 8, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for V
A+ = VD+ = 5V, unless otherwise speci-
fied. Boldface limits apply for T
A = TJ = TMIN to TMAX; all other limits TA = TJ = 25C.
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
V
IN(1)
Logical “1” Input Voltage
V
A+ = VD+ = 5.5V
2.0
V (min)
V
IN(0)
Logical “0” Input Voltage
V
A+ = VD+ = 4.5V
0.8
V (max)
I
IN(1)
Logical “1” Input Current
V
IN = 5V
0.005
1.0
A (max)
LM12(H)458MEL
2.0
I
IN(0)
Logical “0” Input Current
V
IN = 0V
0.005
1.0
A (max)
LM12(H)458MEL
2.0
C
IN
D0–D15 Input Capacitance
6
pF
V
OUT(1)
Logical “1” Output Voltage
V
A+ = VD+ = 4.5V
I
OUT = 360 A
2.4
V (min)
I
OUT = 10 A
4.25
V (min)
V
OUT(0)
Logical “0” Output Voltage
V
A+ = VD+ = 4.5V
0.4
V (max)
I
OUT = 1.6 mA
I
OUT
TRI-STATE Output Leakage Current
V
OUT = 0V
0.01
3.0
A (max)
V
OUT = 5V
0.01
3.0
A (max)
Digital Timing Characteristics (Notes 6, 7, 8, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for V
A+ = VD+ = 5V, tr = tf = 3 ns, and CL =
100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for T
A = TJ = TMIN to TMAX; all
other limits T
A = TJ = 25C.
Symbol
Parameter
Conditions
Typical
Limits
Unit
(See
Figures 8, 9, 10)
(Note 10)
(Note 11)
(Limit)
1, 3
CS or Address Valid to ALE Low
40
ns (min)
Set-Up Time
2, 4
CS or Address Valid to ALE Low
20
ns (min)
Hold Time
5
ALE Pulse Width
45
ns (min)
6
RD High to Next ALE High
35
ns (min)
7
ALE Low to RD Low
20
ns (min)
8
RD Pulse Width
100
ns (min)
9
RD High to Next RD or WR Low
100
ns (min)
10
ALE Low to WR Low
20
ns (min)
11
WR Pulse Width
60
ns (min)
12
WR High to Next ALE High
75
ns (min)
13
WR High to Next RD or WR Low
140
ns (min)
14
Data Valid to WR High Set-Up Time
40
ns (min)
15
Data Valid to WR High Hold Time
30
ns (min)
16
RD Low to Data Bus Out of TRI-STATE
40
10
ns (min)
70
ns (max)
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