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| 型号： | 5962-9957001QRA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封装： | CERDIP-20 |
| 文件页数： | 34/47页 |
| 文件大小： | 764K |
| 代理商： | 5962-9957001QRA |
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TLV2544, TLV2548
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
TLV2544
TLV2548
SDO
1
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state
when CS is high and after the CS falling edge and until the MSB (D15) is presented. The output
format is MSB (D15) first.
When FS is not used (FS = 1 at the falling edge of CS), the MSB (D15) is presented to the SDO pin
after the CS falling edge, and successive data are available at the rising edge of SCLK.
When FS is used (FS = 0 at the falling edge of CS), the MSB (D15) is presented to SDO after the
falling edge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK.
(This is typically used with an active FS from a DSP.)
For conversion and FIFO read cycles, the first 12 bits are result from previous conversion (data)
followed by 4 trailing zeros. The first four bits from SDO for CFR read cycles should be ignored. The
register content is in the last 12 bits. SDO is 3 stated after the 16th bit.
REFM
14
18
I
External reference input or internal reference decoupling.
REFP
15
19
I
External reference input or internal reference decoupling. (Shunt capacitors of 10
F and 0.1 F
between REFP and REFM.) The maximum input voltage range is determined by the difference
between the voltage applied to this terminal and the REFM terminal when an external reference is
used.
VCC
5
I
Positive supply voltage
detailed description
analog inputs and internal test voltages
The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the
command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection
resulting from channel switching.
converter
The TLV2544/48 uses a 12-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1
shows a simplified version of the DAC.
The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
相关PDF资料 |
PDF描述 |
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| TLV2548MJ | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 5962-9957601Q2A | SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, CQCC20 |
| 5962-9957601QPA | SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, CDIP8 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 5962-9957601Q2A | 制造商:Texas Instruments 功能描述:5962-9957601Q2A - Rail/Tube |
| 5962-9957601QPA | 功能描述:数模转换器- DAC 12B1 or 3.5 us DAC Serial InpDual DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| 5962-9957701NXD | 制造商:Texas Instruments 功能描述:THS1206MDAB, ADC, 12BITSERIAL, 6MSPS - Rail/Tube |
| 5962-9958101QXC | 功能描述:LVDS 接口集成电路 RoHS:否 制造商:Texas Instruments 激励器数量:4 接收机数量:4 数据速率:155.5 Mbps 工作电源电压:5 V 最大功率耗散:1025 mW 最大工作温度:+ 85 C 封装 / 箱体:SOIC-16 Narrow 封装:Reel |
| 5962-9958301Q2A | 制造商:Texas Instruments 功能描述:DC DC Cntrlr Single-OUT PWM DC to DC Controller 3.6V to 40V Input 20-Pin LCCC Tube |
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