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参数资料
| 型号： | 5962-9960701TUX |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 25 ns, CDFP36 |
| 封装： | BOTTOM BRAZED, CERAMIC, DFP-36 |
| 文件页数： | 2/15页 |
| 文件大小： | 121K |
| 代理商： | 5962-9960701TUX |
10
t
EFDX
Assumptions & Notes:
1. G < V IL (max). If G > V IH (min) then Q(7:0) will be in three-state for the entire cycle.
2. Either E scenario above can occur.
3 . G high for t AVAV cycle.
A(18:0)
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
W
E
D(7:0)
APPLIED DATA
E
Q(7:0)
tWLQZ
t
ETEF
tWLEF
tDVEF
t
AVAV3
tAVET
t
AVET
tETEF
tEFAX
or
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = V DD/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns
VLOAD = 1.55V
300 ohms
50pF
CMOS
0.5V
V DD-0.05V
10%
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