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参数资料
| 型号： | 5962F0323601QXX |
| 元件分类： | SRAM |
| 英文描述： | 128K X 32 STANDARD SRAM, 15 ns, CQFP68 |
| 封装： | CERAMIC, QFP-68 |
| 文件页数： | 9/16页 |
| 文件大小： | 297K |
| 代理商： | 5962F0323601QXX |
2
PIN NAMES
DEVICE OPERATION
The UT8R128K32 has six control inputs called Enable 1 (E1),
Enable 2 (E2), Write Enable (W), Half-word Enables (HHWE/
LHWE) and Output Enable (G); 17 address inputs, A(16:0); and
32 bidirectional data lines, DQ(15:0). E1 and E2 device enables
control device selection, active, and standby modes. Asserting
E1 and E2 enables the device, causes IDD to rise to its active
value, and decodes the 17 address inputs to select one of 131,072
words in the memory. W controls read and write operations.
During a read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
A(16:0)
Address
W
Write Enable
DQ(31:0)
Data Input/Output
G
Output Enable
E1
Enable (Active Low)
VDD1
Power (1.8V)
E2
Enable (Active High)
VDD2
Power (3.3V)
HHWE
LWHE
High half-word enable
Low half-word enable
VSS
Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Top View
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
V
SS
A0
A1
A2
A3
A4
A5
HHWE
V
SS
LH
WE
W
A6
A7
A8
A9
A10
V
DD1
V
DD1
A11
A12
A13
A14
A15
A16
E1
G
E2
V
DD2
V
SS
NC
V
DD2
V
SS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Figure 2. 15ns SRAM Pinout (68)
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
G
W
E2
E1
LHWE
HHWE
I/O Mode
Mode
X
H
X
DQ(31:16)
3-State
DQ(15:0)
3-State
Standby
X
L
X
DQ(31:16)
3-State
DQ(15:0)
3-State
Standby
L
H
L
H
DQ(31:16)
3-State
DQ(15:0)
Data Out
Low Half-Word
Read
L
H
L
H
L
DQ(31:16)
Data Out
DQ(15:0)
3-State
High Half-Word
Read
L
H
L
DQ(31:16)
Data Out
DQ(15:0)
Data Out
Word Read
X
L
H
L
DQ(31:16)
Data In
DQ(15:0)
Data In
Word Write
X
L
H
L
H
DQ(31:16)
3-State
DQ(15:0)
Data In
Low Half-Word
Write
X
L
H
L
H
L
DQ(31:16)
Data In
DQ(15:0)
3-State
High Half-Word
Write
H
L
X
DQ(31:16)
DQ(15:0)
All 3-State
3-State
X
H
L
H
DQ(31:16)
DQ(15:0)
All 3-State
3-State
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 5962F0521201VXC | 制造商:STMicroelectronics 功能描述:16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLO- W/BUS HOLD, 3.3 VOLT. - Bulk |
| 5962F1023501KXA | 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk |
| 5962F1023502K4A | 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk |
| 5962F1023502K5A | 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk |
| 5962F1023502K6A | 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk |
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