参数资料
型号: 5M2210ZF324I5N
厂商: Altera
文件页数: 27/30页
文件大小: 0K
描述: IC MAX V CPLD 2210 LE 324-FBGA
产品培训模块: Max V Overview
特色产品: MAX? V CPLDs
标准包装: 84
系列: MAX® V
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.0ns
电压电源 - 内部: 1.71 V ~ 1.89 V
逻辑元件/逻辑块数目: 2210
宏单元数: 1700
输入/输出数: 271
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 324-LBGA
供应商设备封装: 324-FBGA(19x19)
包装: 托盘
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–27
Timing Model and Specifications
LVDS and RSDS Output Timing Specifications
Table 3–39 lists the emulated LVDS output timing specifications for MAX V devices.
Table 3–39. Emulated LVDS Output Timing Specifications for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z/5M1270Z/
5M2210Z
Parameter
Mode
Min
C4, C5, I5
Max
Unit
? 10
? 9
? 8
? 7
304
304
304
304
Mbps
Mbps
Mbps
Mbps
Data rate (1) , (2)
t DUTY
Total jitter (3)
t RISE
t FALL
? 6
? 5
? 4
? 3
? 2
? 1
45
304
304
304
304
304
304
55
0.2
450
450
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
UI
ps
ps
Notes to Table 3–39 :
(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the two—the maximum data rate supported by LVDS_E_3R
I/O buffer or 2x (F MAX of the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through
the Quartus II timing analysis of the complete design.
(2) For the input clock pin to achieve 304 Mbps, use I/O standard with V CCIO of 2.5 V and above.
(3) This specification is based on external clean clock source.
May 2011
Altera Corporation
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