参数资料
型号: 5M2210ZF324I5N
厂商: Altera
文件页数: 29/30页
文件大小: 0K
描述: IC MAX V CPLD 2210 LE 324-FBGA
产品培训模块: Max V Overview
特色产品: MAX? V CPLDs
标准包装: 84
系列: MAX® V
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.0ns
电压电源 - 内部: 1.71 V ~ 1.89 V
逻辑元件/逻辑块数目: 2210
宏单元数: 1700
输入/输出数: 271
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 324-LBGA
供应商设备封装: 324-FBGA(19x19)
包装: 托盘
Chapter 3: DC and Switching Characteristics for MAX V Devices
3–29
Timing Model and Specifications
JTAG Timing Specifications
Figure 3–6 shows the timing waveform for the JTAG signals for the MAX V device
family.
Figure 3–6. JTAG Timing Waveform for MAX V Devices
TMS
TDI
t JCH
t JCP
t JCL
t JPSU
t JPH
TCK
TDO
t JPZX
t JPCO
t JPXZ
Signal
to be
t JSSU
t JSH
Captured
t JSZX
t JSCO
t JSXZ
Signal
to be
Driven
Table 3–41 lists the JTAG timing parameters and values for the MAX V device family.
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)
Symbol
t JCP (1)
t JCH
t JCL
t JPSU
t JPH
t JPCO
t JPZX
t JPXZ
t JSSU
t JSH
t JSCO
t JSZX
Parameter
TCK clock period for V CCIO1 = 3.3 V
TCK clock period for V CCIO1 = 2.5 V
TCK clock period for V CCIO1 = 1.8 V
TCK clock period for V CCIO1 = 1.5 V
TCK clock high time
TCK clock low time
JTAG port setup time (2)
JTAG port hold time
JTAG port clock to output (2)
JTAG port high impedance to valid output (2)
JTAG port valid output to high impedance (2)
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Min
55.5
62.5
100
143
20
20
8
10
8
10
Max
15
15
15
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
May 2011
Altera Corporation
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