参数资料
型号: 5P49EE801NDGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/27页
文件大小: 0K
描述: IC CLOCK GENERATOR 28QFN
标准包装: 75
系列: VersaClock™
类型: 时钟发生器
PLL: 带旁路
输入: LVTTL,晶体
输出: LVCMOS,LVDS,LVTTL
电路数: 1
比率 - 输入:输出: 2:7
差分 - 输入:输出: 无/是
频率 - 最大: 150MHz
除法器/乘法器: 是/无
电源电压: 1.71 V ~ 1.89 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-VFQFN 裸露焊盘
供应商设备封装: 28-VFQFPN(4x4)
包装: 管件
其它名称: 800-2524
DATASHEET
VERSACLOCK LOW POWER CLOCK GENERATOR
IDT5P49EE801
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
1
IDT5P49EE801
REV M 072512
Description
The IDT5P49EE801 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to eight differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal. An additional 32kHz
crystal oscillator is available to provide a real time clock or
non-critical performance MHz processor clock.
The IDT5P49EE801 can be programmed through the use
of the I2C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation.
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise. It also may operate in standard spread
sepctrum mode.
There are total seven 8-bit output dividers. One output bank
can be configured to support LVTTL or LVDS. All other
outputs are always set to LVTTL. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
Target Applications
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
Features
Four internal PLLs
Internal non-volatile EEPROM
Internal I2C EEPROM master interface
FAST (400kHz) mode I2C serial interfaces
Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
Output Frequency Ranges: kHz to 120 MHz
Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
8-bit output-divider blocks
One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
– Outputs - 1 pair selectable 3.3 V LVDS
3 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10
μA max in power down mode
– 32kHz clock output active sleep mode
– 100
μA max in sleep mode
1.8V VDD Core Voltage
Available in 28 pin 4x4mm QFN packages
-40 to +85 C Industrial Temp operation
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