参数资料
型号: 5P49EE801NDGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 15/27页
文件大小: 0K
描述: IC CLOCK GENERATOR 28QFN
标准包装: 75
系列: VersaClock™
类型: 时钟发生器
PLL: 带旁路
输入: LVTTL,晶体
输出: LVCMOS,LVDS,LVTTL
电路数: 1
比率 - 输入:输出: 2:7
差分 - 输入:输出: 无/是
频率 - 最大: 150MHz
除法器/乘法器: 是/无
电源电压: 1.71 V ~ 1.89 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-VFQFN 裸露焊盘
供应商设备封装: 28-VFQFPN(4x4)
包装: 管件
其它名称: 800-2524
IDT5P49EE801
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
22
IDT5P49EE801
REV M 072512
0x2D
00
SCR6[1:0]
SCR5[1:0]
SCR4[1:0]
SCR3[1:0]
SRC6[1:0] - OD6 source
00 - off; 10 - PLLC
01 - PLLA; 11 - MHz Reference
SRC5[1:0] - OD5 source
00 - off; 10 - PLLA
01 - PLLC; 11 - PLLB
SRC4[1:0] - OD4 source
00 - off; 10 - MHz Reference
01 - PLLC; 11 - 32kHz Reference
SRC3[1:0] - OD3 source
00 - off; 10 - 32kHz Reference
01 - MHz Reference; 11 - PLLD
0x2E
00
Reserved
SCR2[1:0]
SCR1[1:0]
Reserved
SRC2[1:0] - OD2 source
00 - off; 10 - PLLB
01 - 32kHz Reference; 11 - PLLD
SRC1[1:0] - OD1 source
00 - off; 10 - PLLC
01 - PLLA; 11 - PLLD
0x2F
01
SCR0[1:0]
Reserved
SRC0[1:0] - OD0 source
00 - off; 10 - PLLC
01 - PLLB; 11 - PLLD
0x30
FF
Reserved
0x31
00
PDB[6]
LVDS_ON
OE[6B]
OE[6]
Reserved
PDB[#] - Powerdown OUT#.
PDB[#]=0, OUT# driven low
OE[#] - Output enable OUT#. OE[#]=0,
OUT# tri-stated.
If PDB#=OE#=0, OUT# driven low
LVDS_ON
0 - OUT6A/OUT6B LVCMOS outputs
1 - OUT6A/OUT6B LVDS outputs.
VDDO must be 3.3V
0x32
00
OE[5]
OE[4]
OE[3]
Reserved
OE[2]
OE[1]
Reserved
OE[0]
0x33
00
PDB[5]
PDB[4]
PDB[3]
Reserved
PDB[2]
PDB[1]
Reserved
PDB[0]
0x34
00
REFA[7:0]
Configuration1
(See definitions from Configuration0
above)
0x35
00
FBA[10:3)
0x36
00
Reserved
FBA[2:0)
0x37
00
Reserved
XDIVA
RZA[1:0]
IPA[2:0]
REFSELA
0x38
00
REFB[7:0]
0x39
00
FBB[10:3]
0x3A
00
MOD[4:0]
FBB[2:0]
0x3B
00
MOD[12:5]
0x3C
00
NC[10:3]
0x3D
00
NSS[4:0]
NC[2:0]
0x3E
00
NSS[12:5]
0x3F
40
Reserved
IPB[2:0]
RZB[1:0]
0x40
00
Reserved
REFSELB
SSENB_B
0x41
00
REFC[7:0]
0x42
00
FBC[10:3]
0x43
00
Reserved
FBC[2:0]
0x44
00
FBC2[7:0]
0x45
00
IPC[2:0]
RZC[1:0]
Reserved
XDIV
REFSELC
0x46
00
REFD[7:0]
0x47
00
FBD[10:3]
0x48
00
Reserved
FBD[2:0]
0x49
00
XDIVD
RZD[1:0]
IPD[2:0]
REFSELD[1:0]
0x4A
00
OD0[7:0]
0x4B
00
Reserved
0x4C
00
OD1[7:0]
0x4D
00
OD2[7:0]
0x4E
00
Reserved
Addr
Default
Register
Hex
Value
Bit #
Description
76
5
4
3
2
1
0
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