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参数资料
| 型号： | 5P49EE801NDGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 22/27页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GENERATOR 28QFN |
| 标准包装： | 75 |
| 系列： | VersaClock™ |
| 类型： | 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVTTL，晶体 |
| 输出： | LVCMOS，LVDS，LVTTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:7 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 150MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-VFQFPN（4x4） |
| 包装： | 管件 |
| 其它名称： | 800-2524 |
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IDT5P49EE801
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
4
IDT5P49EE801
REV M 072512
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL. Differential LVDS interface
levels can be generated for OUT4A/OUT4B when connected to VDDO1=3.3V and registers configured
appropriately. Alway completely power up VDD and VDDx prior to applying VDDO power.
Note 2: Default configuration CLK1=Buffered MHz Reference output and CLK2=Buffered 32.768kHz output. All
other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
OUT2
13
O
Adjustable
Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
SEL1*
14
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
OUT1
15
O
Adjustable
Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
VDD
16
Power
Device power supply. Connect to 1.8V.
VDD
17
Power
Device power supply. Connect to 1.8V.
OUT0
18
O
Adjustable
Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
VDDO3
19
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels forOUT0-OUT5.
SCLK
20
I
LVTTL
I2C clock. Logic levels set by VDDO1. 5V tolerant.
OUT6B
21
O
Adjustable
Configurable clock output 6B. Single-ended or differential when
combined with OUT6A. Output voltage levels are controlled by
VDDO1.
OUT6A
22
O
Adjustable
Configurable clock output 6A. Single-ended or differential when
combined with OUT6B. Output voltage levels are controlled by
VDDO1.
SDA
23
I/O
Open Drain
Bidirectional I2C data. Logic levels set by VDDO1. 5V tolerant.
VDD
24
Power
Device power supply. Connect to 1.8V.
VDD
25
Power
Device power supply. Connect to 1.8V.
GND
26
Power
Connect to Ground.
XIN/ REF
27
I
LVTTL
MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input. Maximum reference clock input voltage is
1.8V.
XOUT
28
O
LVTTL
MHz CRYSTAL_OUT -- Reference crystal feedback. Float pin if
using reference input clock.
Pin Name
Pin #
I/O
Pin Type
Pin Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 5P49EE801NDGI8 | 功能描述:时钟发生器及支持产品 VERSACLOCK LOW POWER PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 5P49EE802-007NDGI | 制造商:Integrated Device Technology Inc 功能描述: |
| 5P49EE802NDGI | 功能描述:时钟发生器及支持产品 VERSACLOCK LOW POWER PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 5P49EE802NDGI8 | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN T/R 制造商:Integrated Device Technology Inc 功能描述:28 QFN (4X4MM) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:VERSACLOCK LOW POWER PLL |
| 5P49EE805NDGI | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Quad 28-Pin VFQFPN Tube 制造商:Integrated Device Technology Inc 功能描述:28 QFN (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:PROGRAMMABLE PLL LOW POWER |
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