- 您现在的位置：买卖IC网 > PDF目录97839 > 71M6515H-IGT/F (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY ANALOG CIRCUIT, PQFP64 PDF资料下载
参数资料
| 型号： | 71M6515H-IGT/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 35/60页 |
| 文件大小： | 826K |
| 代理商： | 71M6515H-IGT/F |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
71M6515H
Energy Meter IC
DATA SHEET
JULY 2011
Page: 40 of 60
2005
2011 Teridian Semiconductor Corporation
1.6
A Maxim Integrated Products Brand
STATUS (0x14)
The four bytes in this register reflect the status of the various measurement functions of the 71M6515H. This register is
read only. When a bit in the STMASK register is set, an interrupt (IRQZ) is generated as soon as the corresponding bit in
the STATUS register is set.
Bit 0: This bit (BOOTUP) signals a request from the 71M6515H to the host to be initialized.
Bit 1: This bit (SAGA ), when set, indicates that the voltage applied to phase A has sagged below SAGTHR. See the for SAG
register for a detailed description.
Bit 2: This bit (SAGB), when set, indicates that the voltage applied to phase B has sagged below SAGTHR.
Bit 3: This bit (SAGC), when set, indicates that the voltage applied to phase C has sagged below SAGTHR.
Bit 4: This bit (F0) follows the polarity of the input voltage selected with the F_SELECT bits in the CONFIG register. It
represents a smoothed, filtered and squared copy of the fundamental waveform.
Bit 5: This bit (MAXV), when set, indicates that a voltage greater than the voltage limit defined in the VI_PTHRESHOLD
register had been detected in the previous accumulation interval.
Bit 6: This bit (MAXI), when set, indicates that a current greater than the current limit defined in the VI_PTHRESHOLD
register had been detected in the previous accumulation interval.
Bit 7: This bit (1SECI, toggles every second. It is controlled by the RTC.
Bit 8: This bit (VXEDGE), when set, indicates a change in state of VX comparator. This bit is updated every accumulation
interval.
Bit 9: This bit (DEDGE), when set, indicates a change in state of any selected DIO pin. This bit is updated every
accumulation interval. Pins have to be configured to generate the DEDGE flag using the DIO_INT_CTRL bits in the
D_CONFIG register.
Bit 10: This bit (XOVF), when set, indicates that the host failed to read at least one of the Wh values. Between interrupts
(indicated by the READY bit in the STATUS word), the 71M6515H expects the host to read at least one of the WATTHR_A,
WATTHR_B, or WATTHR_C values.
Bit 11: This bit (READY), when set, indicates that the 71M6515H has fresh output values ready for the host. Setting this bit
in STMASK will enable the hardware interrupt output pin IRQZ.
Bit 14-12: These bits (bit 12 for phase A, bit 13 for phase B, bit 14 for phase C), when set, indicate that the energy
received from element A, B, or C is below the creep threshold defined in the CREEP_THRSHLD register or that the current
in elements A, B, or C is below the threshold defined in bits 15-0 of the START_THRESHLD register. The creep condition
flagged by bits 14-12 of the STATUS register indicates that Wh, VARh, and IRMS measurements of element A, B, or C
have been zeroed out. Consequently, accumulation did not occur.
Bit 15: This bit (CMD_IGNORED), when set, indicates that the 71M6515H ignored the last command received from the
host. The reason can be any type of command incompatibility, e.g. attempts to write to a read-only register.
Bit 16: This bit (PULSEW_ERR), when set, indicates that the pulse generator PULSEW is configured for external (host)
input, but did not receive an update during the previous accumulation interval.
Bit 17: This bit (PULSER_ERR), when set, indicates that the pulse generator PULSER is configured for external (host) input,
but did not receive an update during the previous accumulation interval.
Bit 18: This bit (PULSE3_ERR), when set, indicates that the pulse generator PULSE3 is configured for external (host) input,
but did not receive an update during the previous accumulation interval.
Bit 19: This bit (PULSE4_ERR), when set, indicates that the pulse generator PULSE4 is configured for external (host) input,
but did not receive an update during the previous accumulation interval.
相关PDF资料 |
PDF描述 |
|---|---|
| 7234 | SPECIALTY ANALOG CIRCUIT, CDIP22 |
| 7244 | SPECIALTY ANALOG CIRCUIT, PDIP20 |
| 7250 | SPECIALTY ANALOG CIRCUIT, PDIP16 |
| 73S8009CN-32IMR/F | SPECIALTY ANALOG CIRCUIT, QCC32 |
| 73S8009CN-32IM/F | SPECIALTY ANALOG CIRCUIT, QCC32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 71M6515H-IGTR | 制造商:Maxim Integrated Products 功能描述:71M6515H-IGT - T/REEL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:Metering Systems on a Chip - SoC Energy Meter IC |
| 71M6515H-IGTR/F | 功能描述:计量片上系统 - SoC Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6515H-IGTW/F | 功能描述:计量片上系统 - SoC Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6515H-IGTW1 | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation |
| 71M6515H-IGTWR1 | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation |
发布紧急采购，3分钟左右您将得到回复。