参数资料
型号: 71M6532F-IGT/F
厂商: Maxim Integrated
文件页数: 72/121页
文件大小: 0K
描述: IC ENERGY METER 256KB 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
系列: *

Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
4
4.1
Firmware Interface
I/O RAM and SFR Map – Functional Order
In Table 54, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no
effect, and reading them always returns zero. Reserved bits may be in use and should not be changed from the values given in parentheses.
Writing values other than those shown in parenthesis to reserved bits may have undesirable side effects and must be avoided.
Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected to the
VBAT pin.
This table lists only the SFR registers that are not generic 8051 SFR registers. Bits marked with ? apply to the 71M6531D/F only, bits marked with
? apply to the 71M6532D/F only and should be 0 for the other device.
Table 54: I/O RAM Map in Functional Order
Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Configuration:
CE0 2000 EQU[2:0] CE_E CE10MHZ U
CE1 2001 PRE_SAMPS[1:0] SUM_CYCLES[5:0]
CE2 2002 U CHOP_E[1:0] RTM_E WD_OVF EX_RTC EX_XFR
COMP0 2003 U PLL_OK U U U U U COMP_STAT
CONFIG0 2004 VREF_CAL PLS_INV U CKOUT_E VREF_DIS MPU_DIV[2:0]
CONFIG1 2005 U U ECK_DIS M26MHZ ADC_E MUX_ALT U M40MHZ
VERSION 2006 VERSION[7:0]
CONFIG2 2007 OPT_TXE[1:0] EX_PLL EX_FWCOL FIR_LEN[1:0] OPT_FDC[1:0]
CE3 209D U MUX_DIV[3:0]
CE4 20A7 BOOT_SIZE[7:0]
CE5 20A8 CE_LCTN[7:0]
WAKE 20A9 WAKE_ARM SLEEP LCD_ONLY U WAKE_RES WAKE_PRD[2:0]
TMUX 20AA U TMUX[4:0]
ANACTRL 20AB R (0000) LCD_DAC[2:0] CHOP_I_EN?
CONFIG3 20AC U SEL_IBN? CHOP_IB? U SEL_IAN? CHOP_IA?
CONFIG4 20AD U R (0) R (0) U R (0) R (0)
Interrupts and WD Timer :
INTBITS SFR F8 WD_RST INT6 INT5 INT4 INT3 INT2 INT1 INT0
IFLAGS SFR E8 IE_PLLFALL IE_PLLRISE IE_WAKE IE_PB IE_FWCOL1 IE_FWCOL0 IE_RTC IE_XFER
Flash Memory:
ERASE SFR 94 FLSH_ERASE[7:0]
FLSHCTL SFR B2 PREBOOT SECURE WRPROT_BT WRPROT_CE U FLSH_MEEN FLSH_PWE
FL_BANK SFR B6 U FLBANK[2:0]
PGADR SFR B7 FLSH_PGADR[5:0] U
72
Rev 2
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