参数资料
| 型号： | 71M6541F-DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 38/166页 |
| 文件大小： | 0K |
| 描述： | DEMO BOARD 71M6541F |
| 标准包装： | 1 |
| 系列： | * |
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71M6541D/F/G and 71M6542F/G Data Sheet
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant
1. 8-bit serial modes with parity can be simulated by setting and reading the 9 th bit, using the
control bits TB80 ( S0CON [ 3 ]) and TB81 ( S1CON[3] ) in the S0CON ( SFR 0x98 ) and S1CON ( SFR 0x9B )
registers for transmit and RB81 bit in S1CON[2] for receive operations.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communication in multi-processor systems. In this case, the slave processors have bit
SM20 ( S0CON[5] ) for UART0, or SM21 ( S1CON[5] for UART1, set to 1. When the master processor outputs
the slave’s address, it sets the 9 th bit to 1, causing a serial port receive interrupt in all the slaves. The
slave processors compare the received byte with their address. If there is a match, the addressed slave
clears SM20 or SM21 and receive the rest of the message. The rest of the slave’s ignores the
message. After addressing the slave, the host outputs the rest of the message with the 9 th bit set to 0, so
no additional serial port receive interrupts are generated.
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
Since the TI0 , RI0 , TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided . The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag is cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 19: The S0CON (UART0) Register (SFR 0x98)
Bit
S0CON[7]
Symbol
SM0
Function
The SM0 and SM1 bits set the UART0 mode:
Mode
0
Description
N/A
SM0
0
SM1
0
S0CON[6]
SM1
1
2
3
8-bit UART
9-bit UART
9-bit UART
0
1
1
1
0
1
S0CON[5]
S0CON[4]
S0CON[3]
S0CON[2]
S0CON[1]
S0CON[0]
38
SM20
REN0
TB80
RB80
TI0
RI0
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9 th data bit received. In Mode 1, SM20 is 0,
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
Rev 4
相关PDF资料 |
PDF描述 |
|---|---|
| 71M6543F-DB-CT | DEMO BOARD 71M6543F-DB-CT |
| 72-CNV-5 | CONVERTER RS-232 TO RS-422 5V |
| 72346-001 | 72346-1-SCA-II REC |
| 72347-001LF | CONN RECEPT SCA2 20POS VERT PCB |
| 72436-001LF | 80POS EXT HT. REC SCA-2 |
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