参数资料
型号: 71M6541F-DB
厂商: Maxim Integrated Products
文件页数: 70/166页
文件大小: 0K
描述: DEMO BOARD 71M6541F
标准包装: 1
系列: *
71M6541D/F/G and 71M6542F/G Data Sheet
LCD Drivers (71M6542F/G)
With a maximum of 56 LCD driver pins available, the 71M6542D/F is capable of driving up to 6 x 56 = 336
pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to
42 digits.
LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in 2.5.8.3 Digital I/O
SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O
RAM fields LCD_SEG46[5:0] ( I/O RAM 0x243E[5:0] ) through LCD_SEG50[5:0] ( I/O RAM 0x2442[5:0] ); see
Table 59 . The associated pins function as ICE interface pins, and the ICE functionality overrides the LCD
function whenever ICE_E is pulled high.
Table 59: 71M6542F/G LCD Data Registers for SEG46 to SEG50
SEG
Pin #
46
93
47
92
48
58
49
57
50
56
Always LCD pins, except
Configuration:
when used for ICE interface
or TMUXOUT/TMUX2OUT.
SEG Data Register
2.5.9
EEPROM Interface
The 71M6541D/F/G provides hardware support for either a two-pin or a three-wire (μ-wire) type of
EEPROM interface. The interfaces use the SFR EECTRL ( SFR 0x9F ) and EEDATA (SFR 0x9E)
registers for communication.
2.5.9.1 Two-Pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices and is intended for
use with I 2 C devices. The interface is multiplexed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA)
pins and is selected by setting DIO_EEX[1:0] = 01 ( I/O RAM 0x2456[7:6] ). The MPU communicates with
the interface through the SFR registers EEDATA and EECTRL . If the MPU wishes to write a byte of data
to the EEPROM, it places the data in EEDATA and then writes the Transmit code to EECTRL . This
initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also asserted when
BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the trans-
mission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA . The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the
two-pin interface is selected are shown in Table 60 .
70
Rev 4
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