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参数资料
| 型号： | 71M6542G-IGTR/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | LEAD FREE, LQFP-100 |
| 文件页数： | 83/165页 |
| 文件大小： | 2208K |
| 代理商： | 71M6542G-IGTR/F |
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24
2008–2011 Teridian Semiconductor Corporation
v1.1
Name
Address
RST
Default
WAKE
Default
R/W Description
TMUXRB[2:0]
270A[2:0]
000
R/W The TMUX bits for control of the isolated sensor.
RMT_RD[15:8]
RMT_RD[7:0]
2602[7:0]
2603[7:0]
0
R
The read buffer for 71M6x01 read operations.
RFLY_DIS
210C[3]
0
R/W
Controls how the 71M654x drives the 71M6x01
power pulse. When set, the power pulse is driven
high and low. When cleared, it is driven high
followed by an open circuit flyback interval.
RMTB_E
2709[3]
0
R/W
Enables the isolated remote sensor interface and
re-configures pins IBP-IBN as a balanced pair
digital remote interface.
2.3
Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately
measure energy. The CE calculations and processes include:
Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between
samples caused by the multiplexing scheme).
90
° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on calibration coefficients.
Scaling of samples based on temperature compensation information.
2.3.1
CE Program Memory
The CE program resides in flash memory. Common access to flash memory by the CE and MPU is controlled
by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE
program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass through the
CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed.
For proper operation, the code pass must be completed before the multiplexer cycle ends.
The CE program must begin on a 1 KB boundary of the flash address. The I/O RAM control field
CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) defines which 1 KB boundary contains the CE code. Thus, the first
CE instruction is located at 1024*CE_LCTN[5:0].
2.3.2
CE Data Memory
The CE and MPU share data memory (RAM). Common access to XRAM by the CE and MPU is controlled
by a memory share circuit. The CE can access up to 3 KB of the 3 KB data RAM (XRAM), i.e., from RAM
address 0x0000 to 0x0C00.
The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE.
The MPU reads and writes the XRAM shared between the CE and MPU as the primary means of data
communication between the two processors.
Table 3 shows the CE addresses in XRAM allocated to analog inputs from the AFE.
The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and
accumulators. This hardware is controlled through the I/O RAM control field EQU[2:0], equation assist
(I/O RAM 0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[6]), bit DIO_PW, pulse count assist (I/O RAM
0x2457[7]), and SUM_SAMPS[12:0], accumulation assist (I/O RAM 0x2107[4:0] and 0x2108[7:0]).
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| 71M6543F-DB-CT | 功能描述:开发板和工具包 - 8051 71M6543 Eval Kit RoHS:否 制造商:Silicon Labs 产品:Development Kits 工具用于评估:C8051F960, Si7005 核心: 接口类型:USB 工作电源电压: |
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