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参数资料
| 型号： | 72V845L15PFI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 4K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封装： | TQFP-128 |
| 文件页数： | 1/26页 |
| 文件大小： | 325K |
| 代理商： | 72V845L15PFI8 |
3.3 VOLT CMOS DUAL SyncFIFO
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1,024 x 18, DUAL 2,048 x 18
and DUAL 4,096 x 18
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
1
APRIL 2001
DSC-4295/2
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
OUTPUT
REGISTER
OFFSET
REGISTER
FLAG
LOGIC
FFA/IRA
PAFA
EFA/
ORA
PAEA
HFA/(WXOA)
READ
POINTER
READ
CONTROL
LOGIC
WRITE
CONTROL
LOGIC
WRITE
POINTER
EXPANSION
LOGIC
RESET
LOGIC
WENA
DA0-DA17
LDA
RSA
(
HFA)/WXOA
WXIA
RENA
RCLKA
OEA QA0-QA17
RXOA
RXIA
FLA
WCLKA
INPUT
REGISTER
OUTPUT
REGISTER
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
OFFSET
REGISTER
FLAG
LOGIC
FFB/IRB
PAFB
EFB/ORB
PAEB
HFB/(WXOB)
READ
POINTER
READ
CONTROL
LOGIC
WRITE
CONTROL
LOGIC
WRITE
POINTER
EXPANSION
LOGIC
RESET
LOGIC
WENB
DB0-DB17
LDB
RSB
(
HFB)/WXOB
WXIB
RENB
RCLKB
OEB
QB0-QB17
RXOB
RXIB
FLB
WCLKB
4295 drw 01
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
FEATURES:
The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs
The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs
The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs
The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs
The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs
Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint
Ideal for the following applications:
– Network switching
– Two level prioritization of parallel data
– Bidirectional data transfer
– Bus-matching between 18-bit and 36-bit data paths
– Width expansion to 36-bit per package
– Depth expansion to 8,192 words per package
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full Flags
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedance state
High-performance submicron CMOS technology
Available in a 128-pin thin quad flatpack (TQFP)
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide
synchronous (clocked) First-in, First-out (FIFO) memories designed to run
off a 3.3V supply for exceptionally low power consumption. One dual
IDT72V805/72V815/72V825/72V835/72V845 device is functionally equiva-
lent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single
package with all associated control, data, and flag lines assigned to
independent pins. These devices are very high-speed, low-power First-In,
First-Out (FIFO) memories with clocked read and write controls. These
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| 72V84L15PAG | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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