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参数资料
| 型号： | 72V845L15PFI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 4K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封装： | TQFP-128 |
| 文件页数： | 22/26页 |
| 文件大小： | 325K |
| 代理商： | 72V845L15PFI8 |
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
5
Commercial
Com’l & Ind’l(2)
Commercial
IDT72V805L10
IDT72V805L15
IDT72V805L20
IDT72V815L10
IDT72V815L15
IDT72V815L20
IDT72V825L10
IDT72V825L15
IDT72V825L20
IDT72V835L10
IDT72V835L15
IDT72V835L20
IDT72V845L10
IDT72V845L15
IDT72V845L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency—
100
—
66.7
—
50
MHz
tA
Data Access Time
2
6.5
2
10
2
12
ns
tCLK
Clock Cycle Time
10
—
15
—
20
—
ns
tCLKH
Clock HIGH Time
4.5
—
6
—
8
—
ns
tCLKL
Clock LOW Time
4.5
—
6
—
8
—
ns
tDS
Data Setup Time
3
—
4
—
5
—
ns
tDH
Data Hold Time
0.5
—
1
—
1
—
ns
tENS
Enable Setup Time
3
—
4
—
5
—
ns
tENH
Enable Hold Time
0.5
—
1
—
1
—
ns
tRS
Reset Pulse Width(1)
10
—
15
—
20
—
ns
tRSS
Reset Setup Time
8
—
10
—
12
—
ns
tRSR
Reset Recovery Time
8
—
10
—
12
—
ns
tRSF
Reset to Flag and Output Time
—
15
—
15
—
20
ns
tOLZ
Output Enable to Output in Low-Z(3)
0—0—
0
—
ns
tOE
Output Enable to Output Valid
—
6
3
8
3
10
ns
tOHZ
Output Enable to Output in High-Z(3)
16
38
3
10
ns
tWFF
Write Clock to Full Flag
—
6.5
—
10
—
12
ns
tREF
Read Clock to Empty Flag
—
6.5
—
10
—
12
ns
tPAFA
Clock to Asynchronous Programmable
—
17
—
20
—
22
ns
Almost-Full Flag
tPAFS
Write Clock to Synchronous
—
8
—
10
—
12
ns
Programmable Almost-Full Flag
tPAEA
Clock to Asynchronous Programmable
—
17
—
20
—
22
ns
Almost-Empty Flag
tPAES
Read Clock to Synchronous
—
8
—
10
—
12
ns
Programmable Almost-Empty Flag
tHF
Clock to Half-Full Flag
—
17
—
20
—
22
ns
tXO
Clock to Expansion Out
—
6.5
—
10
—
12
ns
tXI
Expansion In Pulse Width
3
—
6.5
—
8
—
ns
tXIS
Expansion In Setup Time
3
—
5
—
8
—
ns
tSKEW1
Skew time between Read Clock &
5
—
6
—
8
—
ns
Write Clock for
FF/IR and EF/OR
tSKEW2(4)
Skew time between Read Clock &
14
—
18
—
20
—
ns
Write Clock for
PAE and PAF
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V
± 0.3V, TA = -40°C to +85°C)
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Industrial temperature range product for the 15ns speed grade is available as a standard device.
3. Values guaranteed by design, not currently tested.
4. tSKEW2 applies to synchronous
PAE and synchronous PAF only.
30pF*
330
3.3V
510
D.U.T.
4295 drw 03
Figure 1. Output Load
* Includes jig and scope capacitances.
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 1
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