参数资料
型号: 74HC4046AD/T3
厂商: NXP SEMICONDUCTORS
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, PDSO16
封装: SOT-109, SOP-16
文件页数: 4/34页
文件大小: 442K
代理商: 74HC4046AD/T3
1997 Nov 25
12
Philips Semiconductors
Product specication
Phase-locked-loop with VCO
74HC/HCT4046A
Note
1. The parallel value of R1 and R2 should be more than 2.7 k
. Optimum performance is achieved when R1 and/ or
R2 are/is
> 10 k.
Demodulator section
Voltages are referenced to GND (ground = 0 V)
R2
resistor range
3.0
300
k
3.0
note 1
3.0
300
4.5
3.0
300
6.0
C1
capacitor range
40
no
limit
pF
3.0
40
4.5
40
6.0
VVCOIN
operating voltage
range at VCOIN
1.1
1.9
V
3.0
over the range
specied for
R1; for linearity
see Figs 20
and 21
1.1
3.4
4.5
1.1
4.9
6.0
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
V
OTHER
+25
40 to+85 40 to +125
min. typ. max. min. max.
min.
max.
RS
resistor range
50
300
k
3.0
at RS > 300 k
the leakage current can
inuence VDEMOUT
50
300
4.5
50
300
6.0
VOFF
offset voltage
VCOIN to VDEMOUT
±30
mV
3.0
VI =VVCOIN = 1/2 VCC;
values taken over
RS range; see Fig.15
±20
4.5
±10
6.0
RD
dynamic output
resistance at DEMOUT
25
3.0
VDEMOUT = 1/2 VCC
25
4.5
25
6.0
SYM-
BOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
VI
OTHER
+25
40 to +85 40 to +125
min.
typ.
max. min.
max.
min.
max.
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