参数资料
型号: 74HC4046AD/T3
厂商: NXP SEMICONDUCTORS
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, PDSO16
封装: SOT-109, SOP-16
文件页数: 8/34页
文件大小: 442K
代理商: 74HC4046AD/T3
1997 Nov 25
16
Philips Semiconductors
Product specication
Phase-locked-loop with VCO
74HC/HCT4046A
DC CHARACTERISTICS FOR 74HCT
VCO section
Voltages are referenced to GND (ground = 0 V)
Note
1. The parallel value of R1 and R2 should be more than 2.7 k
. Optimum performance is achieved when R1 and/or R2
are/is
> 10 k.
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
VI
OTHER
+25
40 to +85 40 to +125
min
typ.
max
min
max
min.
max.
VIH
HIGH level
input voltage INH
2.0
1.6
2.0
V
4.5
to
5.5
VIL
LOW level
input voltage INH
1.2
0.8
V
4.5
to
5.5
VOH
HIGH level output
voltage VCOOUT
4.4
4.5
4.4
V
4.5
VIH
or
VIL
IO =20 A
VOH
HIGH level output
voltage VCOOUT
3.98
4.32
3.84
3.7
V
4.5
VIH
or
VIL
IO = 4.0 mA
VOL
LOW level output
voltage VCOOUT
0
0.1
V
4.5
VIH
or
VIL
IO =20 A
VOL
LOW level output
voltage VCOOUT
0.15 0.26
0.33
0.4
V
4.5
VIH
or
VIL
IO = 4.0 mA
VOL
LOW level output
voltage C1A,C1B
(test purposes only)
0.40
0.47
0.54
V
4.5
VIH
or
VIL
IO = 4.0 mA
±I
I
input leakage
current
INH, VCOIN
0.1
1.0
A
5.5
VCC
or
GND
R1
resistor range
3.0
300
k
4.5
note 1
R2
resistor range
3.0
300
k
4.5
note 1
C1
capacitor range
40
no
limit
pF
4.5
VVCOIN
operating voltage
range at VCOIN
1.1
3.4
V
4.5
over the
range
specied for
R1; for
linearity see
Figs 20
and 21
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