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参数资料
| 型号： | 74LVC1G57GF,132 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 8/15页 |
| 文件大小： | 0K |
| 描述： | IC CONFIG MULTI-FUNC GATE 6XSON |
| 产品培训模块： | Logic Packages |
| 特色产品： | MicroPak? |
| 标准包装： | 5,000 |
| 系列： | 74LVC |
| 逻辑类型： | 可配置多功能 |
| 电路数： | 1 |
| 输入数： | 3 |
| 施密特触发器输入： | 是 |
| 输出类型： | 单端 |
| 输出电流高，低： | 32mA，32mA |
| 电源电压： | 1.65 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-XFDFN |
| 供应商设备封装： | 6-XSON，SOT891（1x1） |
| 包装： | 带卷 (TR) |
| 其它名称： | 568-9310-2 74LVC1G57GF,132-ND 74LVC1G57GF-H 74LVC1G57GF-H-ND 935282423132 |
CS35L01/03
DS909F1
19
It is important to note that the HD and FHD modes offer significant improvement over traditional Class-D
in idle power dissipation when an external output filter is necessary. This is because the voltage term (V)
is significantly reduced in HD and FHD mode. As can be seen in the equation, this is notable because
reduction in the operating voltage reduces power losses not linearly, but instead exponentially- due to the
voltage squared term (V2). It is also notable that when operated at high output levels, FHD modes also
offers unique improvement in output filter losses, due to reducing the switching frequency (f) at higher out-
put levels.
5.4
Power-Up and Power-Down
When pulled to a logic low state, the SD pin tristates the outputs and shuts down the CS35L01/03 device,
putting it into a low power mode.
5.4.1
Recommended Power-Up Sequence
1. With the SD pin pulled low, apply power to the CS35L01/03 and wait for the power supply to be stable.
2. Set the SD pin high to begin normal operation.
5.4.1.1
Zero-Crossing on Power-Up Functionality
The CS35L01/03 implements an input-signal zero-crossing detection function that is enabled during pow-
er-up. This function is designed to prevent audible artifacts and eliminate any need to mute the amplifier’s
input audio signal during the power-up process.
After a minimum start-up time of tstart, the CS35L01/03 will begin to detect input-signal zero-crossings.
The amplifier will then enable its switching outputs at the time of the first detected input-signal zero-cross-
ing transition. If no input-signal zero-crossing is detected before ttimeout, the zero-crossing function will tim-
eout and the outputs will begin switching immediately.
5.4.2
Recommended Power-Down Sequence
1. Mute the audio supplied to the CS35L01/03.
2. Pull the SD pin low in order to reset the device and put it into the low power mode.
3. The power supply to the CS35L01/03 can now be removed.
OUT+/-
Shut-Down /
Low Power
Mode
tstart
SD
VIH
Device Ready:
Waiting for Zero
Crossing Input
Signal or ttimeout
Internal
Start-Up
VIL
PWM OUT+/-
Active
VBATT or VLDO
IN+/-
ttimeout
Figure 6. Power-Up Timing with Input
Zero-Crossing
Figure 7. Power Up Timing without Input
Zero-Crossing
OUT+/-
Shut-Down /
Low Power
Mode
tstart
SD
VIH
Device Ready: Waiting for Zero
Crossing Input Signal or ttimeout
Internal
Start-Up
VIL
PWM OUT+/-
Active
VBATT or VLDO
IN+/-
ttimeout
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| 74LVC1G57GF-H | 功能描述:逻辑门 3.3V 1G LOW-P CONFIG MULT FCTN RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
| 74LVC1G57GM | 制造商:NXP Semiconductors 功能描述:IC CONFIG MULTI-FUNC GATE XS |
| 74LVC1G57GM,115 | 功能描述:逻辑门 3.3V LP CONFIG GATE RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
| 74LVC1G57GM,132 | 功能描述:逻辑门 3.3V SINGLE 2CHAN RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
| 74LVC1G57GM/S901,1 | 制造商:NXP Semiconductors 功能描述:74LVC1G57GM/XSON6/REEL7//S901 - Tape and Reel |
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