参数资料
型号: 74LVC1G58GM,132
厂商: NXP Semiconductors
文件页数: 3/13页
文件大小: 0K
描述: IC CONFIG MULTI-FUNC GATE 6XSON
产品培训模块: Logic Packages
特色产品: MicroPak?
标准包装: 5,000
系列: 74LVC
逻辑类型: 可配置多功能
电路数: 1
输入数: 3
施密特触发器输入:
输出类型: 单端
输出电流高,低: 32mA,32mA
电源电压: 1.65 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 6-XFDFN
供应商设备封装: 6-XSON,SOT886(1.45x1)
包装: 带卷 (TR)
其它名称: 74LVC1G58GM-H
74LVC1G58GM-H-ND
935277212132
2009-2012 Microchip Technology Inc.
Preliminary
DS41393B-page 17
AR1000 SERIES RESISTIVE TOUCH SCREEN CONTROLLER
4.0
I2CTM COMMUNICATIONS
The AR1021 is an I2C slave device with a 7-bit address
of 0x4D, supporting up to 400 kHz bit rate.
A master (host) device interfaces with the AR1021.
4.1
I2C Hardware Interface
A summary of the hardware interface pins is shown
below in Table 4-1.
M1 Pin
The M1 pin must be connected to VSS to config-
ure the AR1021 for I2C communications.
SCL Pin
The SCL (Serial Clock) pin is electrically
open-drain and requires a pull-up resistor, typi-
cally 2.2 K
to 10 K, from SCL to VDD.
SCL Idle state is high.
SDA Pin
The SDA (Serial Data) pin is electrically
open-drain and requires a pull-up resistor, typi-
cally 2.2K
to 10K, from SDA to VDD.
SDA Idle state is high.
Master write data is latched in on SCL rising
edges.
Master read data is latched out on SCL falling
edges to ensure it is valid during the subsequent
SCL high time.
SDO Pin
The SDO pin is a driven output interrupt to the
master.
SDO Idle state is low.
SDO will be asserted high when the AR1021 has
data ready (touch report or command response)
for the master to read.
TABLE 4-1:
I2C HARDWARE INTERFACE
AR1021 Pin
Description
M1
Connect to VSS to select I2C communications
SCL
Serial Clock to master I2C
SDA
Serial Data to master I2C
SDO
Data ready interrupt output to master
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