参数资料
| 型号： | 78P2351R-DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/15页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR 78P2351R |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 系列： | * |
Design Guidelines for TERIDIAN 78P235x LIUs
Eye Diagram
The Eye Diagram provides a longer-term view of the signal, taking into account the relative time position of
successive pulses. It provides less information about pulse shape but allows a more thorough analysis of the
cumulative effects of wander and jitter. Eye diagrams require the use of DPO mode or other long-term persistence
method to preserve information from the preceding pulses then overlaying them in a continuous fashion. The
timing and pulse width variations are then displayed as a widening of the eye diagram’s traces, which must
remain within the template to meet specification.
“Maximum Eye Diagram” @ 0ft
and
“Small Eye Diagram” @ 225ft
A few words about transmit timing modes in the 78P235x
The 78P235x LIUs use delay lock loop (DLL) technology to track the incoming data and recovery timing. In the
78P235x, there are two different modes in which the integrated CDR is used to recovery the transmit clock. This
section will describe both and their effects on CMI pulse mask testing.
Most transmit timing modes of the 78P235x are synchronous (re-timing) modes where a system reference
clock is provided to the LIU that is source synchronous with the timing of the transmit data source (i.e. SDH
Overhead Processor), E4 Mapper). In this mode of operation, the transmit output is re-timed to eliminate any jitter
caused by clock recovery or serialization.
For application where only data is available at the system (NRZ) interface, a plesiochronous transmit timing
mode is available. In this mode, the recovered transmit clock is used for CMI encoding and pulse shaping.
System Reference
+/- 20ppm for STM1
+/- 15ppm for E4
235x Transmit - Synchronous (re-timing) modes
622 MHz
PLL / VCO
Div/2
TX DATA OUT
Tx Data In
BW ~ 1 MHz
DLL
D
CK
FIFO
De-coupled Tx output exhibits lower phase
jitter due to re-timing with FIFO
+/- 70ppm or better
XO
235x Transmit - Plesiochronous mode
622 MHz
PLL / VCO
BW ~ 1 MHz
Div/2
DLL
TX DATA OUT
Tx Data In
?
?
?
BW = 80 kHz
32 phase taps (100ps )
Direct coupled Tx output will exhibit
high freq. phase jitter
Page 14 of 15
? 2008 Teridian Semiconductor Corp.
Rev 2.1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 78P2351R-IM | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
| 78P2351R-IM/F | 功能描述:接口 - 专用 Serial 155M NRZ to CMI Converter RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
| 78P2351R-IMR | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
| 78P2351R-IMR/F | 功能描述:接口 - 专用 Serial 155M NRZ to CMI Converter RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
| 78P2352 | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Dual Channel OC-3/ STM1-E/ E4 LIU |
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