参数资料
型号: 78P2351R-DB
厂商: Maxim Integrated Products
文件页数: 3/15页
文件大小: 0K
描述: BOARD DEMO FOR 78P2351R
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *

Design Guidelines for TERIDIAN 78P235x LIUs
ANALOG SIGNAL TRACES AND TERMINATIONS
The 78P235x LIUs have differential drivers and receivers. To maintain signal integrity and optimal performance,
all differential traces should be of equal length, parallel to each other, and as short as possible. The impedance of
such traces and terminations should also be well controlled.
For the Reset pin (PORB) , do not tie directly to VCC as this will prevent internal power-on reset. Connect to a
microcontroller for manual reset or de-couple to ground using a 1nF capacitor.
Each LVPECL interface should have a differential trace impedance of 100 ? to the SerDes. For best return loss,
the input termination resistors should be placed within one inch of their 78P235x input pins. LVPECL output
drivers require an external pull-down resistor, which should also be placed near the output pin. See Figure 2 and
Figure 3 for diagrams of recommended terminations of LVPECL I/Os.
NOTES :
1. For DC-coupling, the common mode or bias voltage levels of both ICs must be compatible. Reference product
specifications for more information on bias levels or AC-couple.
2. For E4 applications, DC coupling is required due to the unframed nature of AIS (all ones) signaling in E4.
LVPECL Output (PO)
VCC
from circuit
20
< 20"
< 1"
VCC
Reff
170
50 ohm
to LVPECL
input
from circuit
20
235x IC
PCB
170
50 ohm
< 1"
Figure 2: LVPECL Outputs
LVPECL Input (PI)
3.3V
< 1"
from
transmitting
chip
50 ohm
100
to gates
from
transmitting
chip
50 ohm
82
82
50 ohm
50 ohm
< 1"
to gates
170
170
PCB
235x IC
PCB
235x IC
Figure 3: LVPECL Inputs (DC-coupled and 0.1uF AC-coupled options)
Page 3 of 15
? 2008 Teridian Semiconductor Corp.
Rev 2.1
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