参数资料
型号: 78P2351R-DB
厂商: Maxim Integrated Products
文件页数: 5/15页
文件大小: 0K
描述: BOARD DEMO FOR 78P2351R
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *

Design Guidelines for TERIDIAN 78P235x LIUs
DIGITAL TRACES AND TERMINATIONS
Common board design practices should be applied in the routing of high-speed clock traces. Preferably keep
these signals on the top layer and their length comparable to their associated data path. Its also good practice to
keep clock routes away from the analog side of the LIU as well as it’s associated analog signal routes.
Series source termination is recommended on the parallel (nibble) interface and single-ended clocks. The
termination resistor is placed close to the source driver device. The impedance of the termination resistor, in
combination with the AC output impedance of the source driver, should match the associated trace impedance.
Note the output impedance of the LIU is about 30 ? . The LIU source series termination for a 75 ? trace should
therefore be about 45 ? . This is only appropriate however for a single point to point route, since ideal signal
characteristics only appear at the end point of the signal route. Series termination must not be used for multi-
destination clock routes. External clock distribution buffers or parallel termination should be used for multi-
destination clock routes.
CMOS Digital Output (CO,COZ)
30
40
75 ohm
to
from circuit
Rsrc
< 2"
< 40"
receiving
chip
235x IC
PCB
Figure 6: CMOS Outputs
CMOS Digital Input (CI,CIT,CID)
75 ohm
< 2"
Type CI
VCC
10k
to gates
from
transmitting
75 ohm
Type CIT
to gates
chip
75 ohm
< 2"
Type CID
< 2"
10k
PCB
235x IC
Figure 7: CMOS Inputs
10k
to gates
Page 5 of 15
? 2008 Teridian Semiconductor Corp.
Rev 2.1
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