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参数资料
| 型号： | 78Q2120C09-DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/35页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 78Q2120C |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 系列： | * |
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78Q2120C
10/100BASE-TX
Transceiver
Page: 10 of 35
2009 Teridian Semiconductor Corporation
Rev 1.3
REGISTER DESCRIPTION
The 78Q2120C implements 11 16-bit registers, which are accessible via the MDIO and MDC pins. The supported
registers are shown below in the following table. Attempts to read unsupported registers will be ignored and the
MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the registers except those
which are unique to the 78Q2120C, will respond to the broadcast PHYAD value of ‘00000’. The registers specific
to the 78Q2120C occupy address space MR16-22.
ADDRESS
SYMBOL
NAME
DEFAULT (HEX)
0
MR0
Control
(3100)
1
MR1
Status
(7809)
2
MR2
PHY Identifier 1
000E
3
MR3
PHY Identifier 2
70C9
4
MR4
Auto-Negotiation Advertisement
(01E1)
5
MR5
Auto-Negotiation Link Partner Ability
0000
6
MR6
Auto-Negotiation Expansion
0000
7
MR7
Not Implemented
0000
8-14
MR8-14
Reserved
0000
15
MR15
Not Implemented
0000
16
MR16
Vendor Specific
(0140)
17
MR17
Interrupt Control/Status Register
0000
18
MR18
Diagnostic Register
0000
19
MR19
Transceiver Control
4XXX
20-22
MR20-MR22
Reserved
0000
Legend:
TYPE DESCRIPTION
R
Readable by management.
W
Writeable by management.
SC
Writeable by management. Self
Clearing.
RC
Readable by management.
Cleared upon a read operation.
0/1
Default value upon power up or
reset.
(0/1)
Default value dependent on pin
settings. The value in bracket
indicates typical case.
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