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参数资料
| 型号： | 78Q2120C09-DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/35页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 78Q2120C |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 系列： | * |
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78Q2120C
10/100BASE-TX
Transceiver
Page: 17 of 35
2009 Teridian Semiconductor Corporation
Rev 1.3
MR16: Vendor Specific Register (continued)
Bit
Symbol
Type
Default
Description
16.1
PCSBP
R/W
(0)
PCS Bypass Mode: When set, the 100Base-TX PCS and scrambling/
descrambling functions are bypassed. Scrambled 5-bit code groups
for transmission are applied to the TX_ER, TXD[3:0] pins and
received on the RX_ER, RXD[3:0] pins. The RX_DV and TX_EN
signals are not valid in this mode. PCSBP mode is valid only when
100Base-TX mode is enabled and auto-negotiation is disabled.
16.0
RXCC
R/W
0
Receive Clock Control: This function is valid only in 100Base-TX
mode. When set to ‘1’, the RX_CLK signal will be held low when
there is no data being received (to save power). The RX_CLK signal
will restart 1 clock cycle before the assertion of RX_DV and be shut
off 64 clock cycles after RX_DV goes low. RXCC is disabled when
the loopback mode is enabled (MR0.14 is high). This bit should be
kept at logic zero when PCS Bypass mode is used.
MR17: Interrupt Control/Status Register
The Interrupt Control/Status Register provides the means for controlling and observing events which trigger an
interrupt on the INTR pin. This register can also be used in a polling mode via the MII Serial Interface as a means
to observe key events within the PHY via one register address. Bits 0 through 7 are status bits, which are each
set to logic one based upon an event. These bits are cleared after the register is read. Bits 8 through 15 of this
register, when set to logic one, enable their corresponding bit in the lower byte to signal an interrupt on the INTR
pin. The level of this interrupt can be set via the MR16.14 (INPOL) bit.
BIT
SYMBOL
TYPE DEFAULT DESCRIPTION
17.15
JABBER_IE
R/W
0
Jabber Interrupt Enable
17.14
RXER_IE
R/W
0
Receive Error Interrupt Enable
17.13
PRX_IE
R/W
0
Page Received Interrupt Enable
17.12
PDF_IE
R/W
0
Parallel Detect Fault Interrupt Enable
17.11
LP-ACK_IE
R/W
0
Link Partner Acknowledge Interrupt Enable
17.10
LS_CHG_IE
R/W
0
Link Status Change Interrupt Enable
17.9
RFAULT_IE
R/W
0
Remote Fault Interrupt Enable
17.8
ANEG-
COMP_IE
R/W
0
Auto-Negotiation Complete Interrupt Enable
17.7
JAB_INT
RC
0
Jabber Interrupt:
This bit is set high when a Jabber event is
detected by the 10Base-T circuitry.
17.6
RXER_INT
RC
0
Receive Error Interrupt: This bit is set high when the RX_ER signal
transitions high.
17.5
PRX_INT
RC
0
Page Received Interrupt: This bit is set high when a new page has
been received from the link partner during auto-negotiation.
17.4
PDF_INT
RC
0
Parallel Detect Fault Interrupt: This bit is set high by the auto-
negotiation logic when a parallel detect fault condition is indicated.
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