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| 型号： | 843002AKI-40LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | XO, clock |
| 英文描述： | 175 MHz, OTHER CLOCK GENERATOR, QCC32 |
| 封装： | 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32 |
| 文件页数： | 11/24页 |
| 文件大小： | 742K |
| 代理商： | 843002AKI-40LF |
ICS843002I-40
175MHZ, FEMTOCLOCKS VCXO BASED SONET/SDH JITTER ATTENUATOR
IDT / ICS VCXO BASED SONET/SDH JITTER ATTENUATOR
19
ICS843002AKI-40 REV. B APRIL 27, 2009
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage
of VCCO – 2V.
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CCO
V
CCO - 2V
Q1
RL
50
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