参数资料
型号: 843002AKI-40LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: XO, clock
英文描述: 175 MHz, OTHER CLOCK GENERATOR, QCC32
封装: 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32
文件页数: 9/24页
文件大小: 742K
代理商: 843002AKI-40LF
ICS843002I-40
175MHZ, FEMTOCLOCKS VCXO BASED SONET/SDH JITTER ATTENUATOR
IDT / ICS VCXO BASED SONET/SDH JITTER ATTENUATOR
17
ICS843002AKI-40 REV. B APRIL 27, 2009
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must
be taken with the package and load capacitance (CL). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with
the package, it is recommended that a metal-canned package like
HC49 be used. Generally, a metal-canned package has a larger
pulling range than a surface mounted device (SMD). For crystal
selection information, refer to the VCXO Crystal Selection
Application Note.
The crystal’s load capacitance CL characteristic determines it
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (CTUNE).
If the crystal CL is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal (CL) is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
reduced. The correct value of CL is dependant on the
characteristics of the VCXO. The recommended CL in the Crystal
Parameter Table balances the tuning range by centering the
tuning curve.
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS
and CP values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. For other configurations, refer to the Loop Filter
Component Selection for VCXO Based PLLs Application Note.
The crystal and external loop
filter components should be
kept as close as possible to the
device. Loop filter and crystal
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not run
underneath the device, loop
filter or crystal components.
VCXO Characteristics Table
VCXO-PLL Loop Bandwidth Selection Table
Crystal Characteristics
LF0
LF1
ISET
XTAL_IN
XTAL_OUT
RS
C
S
C
P
R
SET
C
TUNE
C
TUNE
19.44MHz
Symbol
Parameter
Typical
Units
kVCXO
VCXO Gain
5800
Hz/V
CV_LOW
Low Varactor Capacitance
12.6
pF
CV_HIGH
High Varactor Capacitance
24.5
pF
Bandwidth
Crystal Frequency (MHz)
RS (k)CS (F)
CP (F)
RSET (k)
10Hz (Low)
19.44
5
1.0
0.10
9.5
70Hz (Mid)
19.44
10
1.0
0.01
4.75
100Hz (High)
19.44
15
1.0
0.01
4.75
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Fundamental
fN
Frequency
19.44
MHz
fT
Frequency Tolerance
±20
ppm
fS
Frequency Stability
±20
ppm
Operating Temperature Range
-40
+85
0C
CL
Load Capacitance
12
pF
CO
Shunt Capacitance
4
pF
CO / C1
Pullability Ratio
220
240
ESR
Equivalent Series Resistance
50
Drive Level
1mW
Aging @ 25 0C
±3 per year
ppm
相关PDF资料
PDF描述
84364-5 22 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE
84364-7 12 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE
84364-8 12 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE
84364-9 34 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE
844256BGT 622.08 MHz, OTHER CLOCK GENERATOR, PDSO24
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