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| 型号： | 843002AKI-40LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | XO, clock |
| 英文描述： | 175 MHz, OTHER CLOCK GENERATOR, QCC32 |
| 封装： | 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32 |
| 文件页数： | 5/24页 |
| 文件大小： | 742K |
| 代理商： | 843002AKI-40LF |
ICS843002I-40
175MHZ, FEMTOCLOCKS VCXO BASED SONET/SDH JITTER ATTENUATOR
IDT / ICS VCXO BASED SONET/SDH JITTER ATTENUATOR
13
ICS843002AKI-40 REV. B APRIL 27, 2009
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as many
vias connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz
copper via barrel plating. This is desirable to avoid any solder
wicking inside the via during the soldering process which may
result in voids in solder between the exposed pad/slug and the
thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDER
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
THERMAL VIA
相关PDF资料 |
PDF描述 |
|---|---|
| 84364-5 | 22 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE |
| 84364-7 | 12 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE |
| 84364-8 | 12 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE |
| 84364-9 | 34 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE |
| 844256BGT | 622.08 MHz, OTHER CLOCK GENERATOR, PDSO24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 843002AKI-40LFT | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 843002AKI-40T | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 843002AKI-41 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 843002AKI-41LF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 843002AKI-41LFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Generator Dual 32-Pin VFQFPN EP T/R 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK GEN DUAL 32PIN VFQFPN - Tape and Reel |
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