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| 型号： | 89HPES12T3G2 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 12-Lane 3-Port Gen2 PCI Express Switch |
| 中文描述： | 12巷3端口第二代的PCI Express开关 |
| 文件页数： | 2/31页 |
| 文件大小： | 291K |
| 代理商： | 89HPES12T3G2 |
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September 4, 2007
IDT 89HPES12T3G2 Data Sheet
*Notice: The information in this document is subject to change without notice
A
–
–
Unused SerDes are disabled.
Supports Advanced Configuration and Power Interface Spec-
ification, Revision 2.0 (ACPI) supporting active link state
◆
Testability and Debug Features
–
Built in Pseudo-RandomBit Stream(PRBS) generator
–
Numerous SerDes test modes
–
Ability to read and write any internal register via the SMBus
–
Ability to bypass link training and force any link into any mode
–
Provides statistics and performance counters
◆
Nine General Purpose Input/Output Pins
–
Each pin may be individually configured as an input or output
–
Each pin may be individually configured as an interrupt input
–
Some pins have selectable alternate functions
◆
Packaged in a 19mm x 19mm, 324-ball BGA with 1mm
ball spacing
Produc t Desc ription
Utilizing standard PCI Express interconnect, the PES12T3G2
provides the most efficient fan-out solution for applications requiring high
throughput, low latency, and simple board layout with a mnimum
number of board layers. It provides 12 GBps (96 Gbps) of aggregated,
full-duplex switching capacity through 12 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 Gbps of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES12T3G2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES12T3G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limted connectivity.
Figure 2 I/O Expansion Application
MMemory
Processor
North
Bridge
PES12T3G2
I/O
10GbE
I/O
10GbE
I/O
SATA
PCI Express
Slot
Processor
x4
x4
x4
x4
S MBus Interface
The PES12T3G2 contains two SMBus interfaces. The slave inter-
face provides full access to the configuration registers in the
PES12T3G2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES12T3G2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROMfromwhich data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
As shown in Figure 2, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 2(a), the master and slave SMBuses are tied together and the
PES12T3G2 acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES12T3G2 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or mcro controller and may
not support SMBus arbitration. To support these systems, the
PES12T3G2 may be configured to operate in a split configuration as
shown in Figure 2(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES12T3G2 supports reading and writing of the serial
EEPROMon the master SMBus via the slave SMBus, allowing in
systemprogrammng of the serial EEPROM.
Bit
S lave
S MBus
Address
Master
S MBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
6
1
0
7
1
1
Table 1 Master and Slave SMBus Address Assignment
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 89HPES12T3G2ZABC | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES12T3G2ZABC8 | 功能描述:开关 IC - 各种 RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
| 89HPES12T3G2ZABCG | 功能描述:接口-I/O扩展器 RoHS:否 制造商:NXP Semiconductors 逻辑系列: 输入/输出端数量: 最大工作频率:100 kHz 工作电源电压:1.65 V to 5.5 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:HVQFN-16 封装:Reel |
| 89HPES12T3G2ZABCG8 | 功能描述:开关 IC - 各种 RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
| 89HPES12T3G2ZBBC | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:托盘 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:84 |
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