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参数资料
| 型号： | 89HPES12T3G2 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 12-Lane 3-Port Gen2 PCI Express Switch |
| 中文描述： | 12巷3端口第二代的PCI Express开关 |
| 文件页数： | 6/31页 |
| 文件大小： | 291K |
| 代理商： | 89HPES12T3G2 |
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September 4, 2007
IDT 89HPES12T3G2 Data Sheet
A
S ignal
Type
Name/Desc ription
CCLKDS
I
Common Clock Downstream.
The assertion of this pin indicates that all
downstreamports are using the same clock source as that provided to
downstreamdevices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstreamports.
The value may be overridden by modifying the SCLK bit in each down-
streamport’s PCIELSTS register.
CCLKUS
I
Common Clock Upstream.
The assertion of this pin indicates that the
upstreamport is using the same clock source as the upstreamdevice. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstreamport. The value may be overridden by
modifying the SCLK bit in the P0_PCIELSTS register.
MSMBSMODE
I
Master SMBus Slow Mode.
The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
PERSTN
I
Fundamental Reset.
Assertion of this signal resets all logic inside
PES12T3G2 and initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt.
When this signal is asserted during a PCI Express fundamental
reset, PES12T3G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[2:0]
I
Switch Mode.
These configuration pins determne the PES12T3G2 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROMinitialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
Table 5 System Pins
S ignal
Type
Name/Desc ription
JTAG_TCK
I
JTAG Clock
. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the systemclock with a nomnal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input
. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 6 Test Pins (Part 1 of 2)
相关PDF资料 |
PDF描述 |
|---|---|
| 89HPES12T3G2ZABC | 12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES12T3G2ZABCG | 12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES16NT2 | 16-Lane 2-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES16T4G2 | 16-Lane 4-Port Gen2 PCI Express Switch |
| 89HPES16T4G2ZABX | 16-Lane 4-Port Gen2 PCI Express Switch |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 89HPES12T3G2ZABC | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES12T3G2ZABC8 | 功能描述:开关 IC - 各种 RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
| 89HPES12T3G2ZABCG | 功能描述:接口-I/O扩展器 RoHS:否 制造商:NXP Semiconductors 逻辑系列: 输入/输出端数量: 最大工作频率:100 kHz 工作电源电压:1.65 V to 5.5 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:HVQFN-16 封装:Reel |
| 89HPES12T3G2ZABCG8 | 功能描述:开关 IC - 各种 RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
| 89HPES12T3G2ZBBC | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:托盘 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:84 |
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