参数资料
型号: 89HPES16T4G2
厂商: Integrated Device Technology, Inc.
英文描述: 16-Lane 4-Port Gen2 PCI Express Switch
中文描述: 16巷4端口第二代的PCI Express开关
文件页数: 2/32页
文件大小: 305K
代理商: 89HPES16T4G2
2 of 32
September 4, 2007
IDT 89HPES16T4G2 Data Sheet
*Notice: The information in this document is subject to change without notice
A
Power Management
Utilizes advanced low-power design techniques to achieve low
typical power consumption
Support PCI Express Power Management Interface specifica-
tion (PCI-PM2.0)
Unused SerDes are disabled.
Supports Advanced Configuration and Power Interface Spec-
ification, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
Built in Pseudo-RandomBit Stream(PRBS) generator
Numerous SerDes test modes
Ability to read and write any internal register via the SMBus
Ability to bypass link training and force any link into any mode
Provides statistics and performance counters
Sixteen General Purpose Input/Output Pins
Each pin may be individually configured as an input or output
Each pin may be individually configured as an interrupt input
Some pins have selectable alternate functions
Packaged in a 23mm x 23mm, 288-ball BGA with 1mm
ball spacing
Produc t Desc ription
Utilizing standard PCI Express interconnect, the PES16T4G2
provides the most efficient fan-out solution for applications requiring high
throughput, low latency, and simple board layout with a mnimum
number of board layers. It provides 16 GBps (128 Gbps) of aggregated,
full-duplex switching capacity through 16 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 Gbps of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES16T4G2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES16T4G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limted connectivity.
Figure 2 I/O Expansion Application
S MBus Interface
The PES16T4G2 contains two SMBus interfaces. The slave inter-
face provides full access to the configuration registers in the
PES16T4G2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES16T4G2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROMfromwhich data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Bit
S lave
S MBus
Address
Master
S MBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
6
1
0
7
1
1
Table 1 Master and Slave SMBus Address Assignment
MMemory
Processor
North
Bridge
PES16T4G2
I/O
10GbE
I/O
10GbE
I/O
SATA
I/O
SATA
PCI Express
Slot
Processor
x4
x4
x4
x4
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