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参数资料
型号： 89HPES16T4G2
厂商： Integrated Device Technology, Inc.
英文描述： 16-Lane 4-Port Gen2 PCI Express Switch
中文描述： 16巷4端口第二代的PCI Express开关
文件页数： 7/32页
文件大小： 305K
代理商： 89HPES16T4G2
7 of 32
September 4, 2007
IDT 89HPES16T4G2 Data Sheet
A
S ignal
Type
Name/Desc ription
JTAG_TCK
I
JTAG Clock
. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the systemclock with a nomnal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input
. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output
. This is the serial data shifted out fromthe boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode
. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset
. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
S ignal
Type
Name/Desc ription
REFRES0
I/O
Port 0 External Reference Resistor.
Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm+/- 1% resis-
tor should be connected fromthis pin to ground.
REFRES2
I/O
Port 2 External Reference Resistor.
Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm+/- 1% resis-
tor should be connected fromthis pin to ground.
REFRES4
I/O
Port 4 External Reference Resistor.
Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm+/- 1% resis-
tor should be connected fromthis pin to ground.
REFRES6
I/O
Port 6 External Reference Resistor.
Provides a reference for the Port 6
SerDes bias currents and PLL calibration circuitry. A 3 kOhm+/- 1% resis-
tor should be connected fromthis pin to ground.
V
DD
CORE
I
Core V
DD.
Power supply for core logic.
V
DD
I/O
I
I/O V
DD.
LVTTL I/O buffer power supply.
V
DD
PEA
I
PCI Express Analog Power.
Serdes analog power supply (1.0V).
V
DD
PEHA
I
PCI Express Analog High Power.
Serdes analog power supply (2.5V).
V
DD
PETA
I
PCI Express Transmitter Analog Voltage.
Serdes transmtter analog
power supply (1.0V).
V
SS
I
Ground.
Table 7 Power, Ground, and SerDes Resistor Pins
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