参数资料
型号: 89HPES16T4G2
厂商: Integrated Device Technology, Inc.
英文描述: 16-Lane 4-Port Gen2 PCI Express Switch
中文描述: 16巷4端口第二代的PCI Express开关
文件页数: 6/32页
文件大小: 305K
代理商: 89HPES16T4G2
6 of 32
September 4, 2007
IDT 89HPES16T4G2 Data Sheet
A
GPIO[11]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstreamport 6.
GPIO[12]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[13]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[14]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[15]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
S ignal
Type
Name/Desc ription
CCLKDS
I
Common Clock Downstream.
The assertion of this pin indicates that all
downstreamports are using the same clock source as that provided to
downstreamdevices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstreamports.
The value may be overridden by modifying the SCLK bit in each down-
streamport’s PCIELSTS register.
CCLKUS
I
Common Clock Upstream.
The assertion of this pin indicates that the
upstreamport is using the same clock source as the upstreamdevice. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstreamport. The value may be overridden by
modifying the SCLK bit in the P0_PCIELSTS register.
MSMBSMODE
I
Master SMBus Slow Mode.
The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
PERSTN
I
Fundamental Reset.
Assertion of this signal resets all logic inside
PES16T4G2 and initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt.
When this signal is asserted during a PCI Express fundamental
reset, PES16T4G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[2:0]
I
Switch Mode.
These configuration pins determne the PES16T4G2 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROMinitialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
Table 5 System Pins
S ignal
Type
Name/Desc ription
Table 4 General Purpose I/O Pins (Part 2 of 2)
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