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参数资料
| 型号： | 935264570557 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件页数： | 14/36页 |
| 文件大小： | 145K |
| 代理商： | 935264570557 |
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2000 Nov 17
21
Philips Semiconductors
Preliminary specication
1394 SBP-2 link layer controller
SAA7356HL
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 0; note 1; see Fig.11
t0
cycle time
40
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
30
ns
t2
DMA_REQ de-assert from DMA_WRITE assert
(multi-word DMA)
30
ns
t3
DMA_REQ de-assert from DMA_READ assert
(multi-word DMA)
30
ns
t4
DMA_REQ assert after DMA_ACK de-assert
0
ns
t5
write data set-up
20
ns
t6
write data hold
0
ns
t7
DMA_WRITE active pulse duration
20
ns
t8
read data stable after DMA_READ active
15
ns
t9
read data 3-state after DMA_READ inactive
25
30
ns
t10
DMA_WRITE active pulse duration
20
ns
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 1; note 1; see Fig.12
t0
cycle time
40
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
30
ns
t2
DMA_REQ de-assert from DMA_WRITE assert
(multi-word DMA)
30
ns
t3
DMA_REQ assert after DMA_ACK de-assert
0
ns
t4
read data stable after DMA_ACK assert
15
ns
t5
read data 3-state after DMA_ACK inactive
25
30
ns
t6
write data set-up
20
ns
t7
write data hold
0
ns
t8
DMA_WRITE active pulse width
20
ns
t9
DMA_ACK active pulse width
20
ns
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 2; note 1; see Fig.13
t0
cycle time
40
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
30
ns
t2
DMA_REQ assert after DMA_ACK de-assert
0
ns
t3
write data set-up
20
ns
t4
write data hold
0
ns
t5
DMA_ACK active pulse duration during data write
20
ns
t6
read data stable after DMA_ACK assert
15
ns
t7
read data 3-state after DMA_ACK de-assert
25
30
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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