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参数资料
| 型号： | 935269556118 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件页数： | 11/12页 |
| 文件大小： | 86K |
| 代理商： | 935269556118 |
Philips Semiconductors
Product data
PCK2057
70 – 190 MHz I2C differential 1:10 clock driver
2001 Jun 12
8
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPD
Propagation delay time
Test mode/CLK to any output
—
3.7
—
ns
tPHL
HIGH-to-LOW level propagation delay time
SCL to SDA (acknowledge)
—
500 1
—
ns
ten
Output enable time
Test mode/SDA to Y output
—
85
—
ns
tdis
Output disable time
Test mode/SDA to Y output
—
35
—
ns
tjit(per)
Jitter (period); see Figure 4
100 MHz to 167 MHz
–75
—
75
ps
tjit(cc)
Jitter (cycle-to-cycle); see Figure 5
100 MHz to 167 MHz
–75
—
75
ps
tjit(hper)
Half-period jitter; see Figure 6
100 MHz to 167 MHz
–90
—
90
ps
t
Static phase offset; see Figure 1
133 MHz/VID on CLK = 0.71 V
220
—
450
ps
t
Static phase offset; see Figure 1
167 MHz/VID on CLK = 0.71 V
140
—
270
ps
tslr(o)
Output clock slew rate; see Figure 3
terminated with 120
/14 pF
1
—
2
V/ns
tsk(o)
Output skew; see Figure 2
—
75
ps
SSC modulation frequency
30
—
33.3
kHz
SSC clock input frequency deviation
0.00
—
–0.50
%
NOTE:
1. This time is for a PLL frequency of 100 MHz.
AC WAVEFORMS
SW00882
t(O) = Σ
1
n =N
t(O)n
N
t(O)n
t(O)n + 1
(N is a large number of samples)
CLK
FBIN
Figure 1. Static phase offset
SW00883
tsk(O)
Yx
Yx, FBOUT
Figure 2. Output skew
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