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| 型号： | 935270050128 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件页数： | 14/55页 |
| 文件大小： | 706K |
| 代理商： | 935270050128 |
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Philips Semiconductors
SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
21 of 52
9397 750 10985
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the THR, providing that the THR or TSR is empty. The THR empty ag in the LSR
register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty ag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C654/654D and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On
the falling edge of a start or false start bit, an internal receiver counter starts counting
clocks at the 16
× clock rate. After 7-12 clocks, the start bit time should be shifted to
the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0
it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA-INTD output pins in the 16 mode, or on wire-OR IRQ
output pin in the 68 mode.
Table 9:
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7]
CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C654/654D issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
6
IER[6]
RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C654/654D issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
5
IER[5]
Xoff interrupt.
Logic 0 = Disable the software ow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software ow control, receive Xoff interrupt. See
Section 6.7 “Software ow control” for details.
4
IER[4]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See Section 6.13 “Sleep mode” for details.
3
IER[3]
Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
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