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参数资料
| 型号： | 935270050128 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件页数： | 9/55页 |
| 文件大小： | 706K |
| 代理商： | 935270050128 |
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Philips Semiconductors
SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
17 of 52
9397 750 10985
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
CLKSEL pin. A logic 1 on CLKSEL will set the 1
× clock default, whereas logic 0 will
set the 4
× clock default table. Following the default clock rate selection during
initialization, the rate tables can be changed by the internal register MCR[7]. Setting
MCR[7] to a logic 1 when CLKSEL is a logic 1 provides an additional divide-by-4,
whereas setting MCR[7] to a logic 0 only divides by 1. (See Table 7 and Figure 7.)
Customized Baud Rates can be achieved by selecting the proper divisor values for
the MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired nal baud rate. The example in
Table 7 shows the two selectable baud rate tables available when using a
7.3728 MHz crystal.
Table 7:
Baud rate generator programming table using a 7.3728 MHz clock
Output baud rate
User
16
× clock divisor
DLM
program value
(HEX)
DLL
program value
(HEX)
MCR[7] = 1
MCR[7] = 0
Decimal
HEX
50
200
2304
900
09
00
300
1200
384
180
01
80
600
2400
192
C0
00
C0
1200
4800
96
60
00
60
2400
9600
48
30
00
30
4800
19.2 k
24
18
00
18
9600
38.4 k
12
0C
00
0C
19.2 k
76.8 k
6
06
00
06
38.4 k
153.6 k
3
03
00
03
57.6 k
230.4 k
2
02
00
02
115.2 k
460.8 k
1
01
00
01
Fig 7.
Baud rate generator circuitry.
BAUD RATE
GENERATOR
LOGIC
BAUDOUT
MCR[7] = 1
MCR[7] = 0
DIVIDE-BY-1
LOGIC
DIVIDE-BY-4
LOGIC
CLOCK
OSCILLATOR
LOGIC
002aaa208
XTAL1
XTAL2
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