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参数资料
| 型号： | 935270050128 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件页数： | 6/55页 |
| 文件大小： | 706K |
| 代理商： | 935270050128 |
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Philips Semiconductors
SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
14 of 52
9397 750 10985
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
interrupt is generated whenever the Receive Holding Register (RHR) has not been
read following the loading of a character or the receive trigger level has not been
reached. (For a description of this timing, see Section 6.6 “Hardware ow control”.)
6.6 Hardware ow control
When automatic hardware ow control is enabled, the SC16C654/654D monitors the
CTS pin for a remote buffer overow indication and controls the RTS pin for local
buffer overows. Automatic hardware ow control is selected by setting EFR[6] (RTS)
and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating
a ow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C654/654D will suspend TX transmissions as soon as the stop bit of the
character in process is shifted out. Transmission is resumed after the CTS input
returns to a logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C654/654D will continue to accept data until the receive FIFO is full.
6.7 Software ow control
When software ow control is enabled, the SC16C654/654D compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C654/654D will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) ags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C654/654D will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C654/654D will resume operation
and clear the ags (ISR[4]). The SC16C654/654D offers a special Xon mode via
MCR[5]. The initialized default setting of MCR[5] is a logic 0. In this state, Xoff and
Xon will operate as dened above. Setting MCR[5] to a logic 1 sets a special
operational mode for the Xon function. In this case, Xoff operates normally, however,
transmission (Xon) will resume with the next character received, i.e., a match is
declared simply by the receipt of an incoming (RX) character.
Reset initially sets the contents of the Xon/Xoff 8-bit ow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software ow
control. Different conditions can be set to detect Xon/Xoff characters and
Table 6:
RX trigger levels
Selected trigger level
(characters)
INT pin activation
Negate RTS or
send Xoff
(characters)
Assert RTS or
send Xon
(characters)
8
16
0
16
56
7
56
60
15
60
55
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