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参数资料
| 型号： | 935270050128 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件页数： | 7/55页 |
| 文件大小： | 706K |
| 代理商： | 935270050128 |
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Philips Semiconductors
SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
15 of 52
9397 750 10985
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C654/654D compares two consecutive receive characters with two software
ow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described ow control mechanisms, ow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overlling and ow control needs to be executed,
the SC16C654/654D automatically sends an Xoff message (when enabled) via the
serial TX output to the remote modem. The SC16C654/654D sends the Xoff1,2
characters as soon as received data passes the programmed trigger level. To clear
this condition, the SC16C654/654D will transmit the programmed Xon1,2 characters
as soon as receive data drops below the programmed trigger level.
6.8 Special feature software ow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software ow control should be turned off when using this special
mode by setting EFR[0-3] to a logic 0.
The SC16C654/654D compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table 8) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] dene the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0-1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
6.9 Xon any feature
A special feature is provided to return the Xoff ow control to the inactive state
following its activation. In this mode, any RX character received will return the Xoff
ow control to the inactive state so that transmissions may be resumed with a remote
buffer. This feature is more fully dened in Section 6.7 “Software ow control”.
6.10 Hardware/software and time-out interrupts
Three special interrupts have been added to monitor the hardware and software ow
control. The interrupts are enabled by IER[5-7]. Care must be taken when handling
these interrupts. Following a reset, the transmitter interrupt is enabled, the
SC16C654/654D will issue an interrupt to indicate that the Transmit Holding Register
is empty. This interrupt must be serviced prior to continuing operations. The LSR
register provides the current singular highest priority interrupt only. It could be noted
that CTS and RTS interrupts have lowest interrupt priority. A condition can exist
where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).
Only after servicing the higher pending interrupt will the lower priority CTS/TRS
interrupt(s) be reected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
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