参数资料
| 型号： | 93LC46/P |
| 厂商： | Microchip Technology |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 1KBIT 1MHZ 8DIP |
| 标准包装： | 60 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1K（128 x 8 或 64 x 16） |
| 速度： | 1MHz |
| 接口： | Microwire 3 线串行 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 1450 (CN2011-ZH PDF) |
93LC46/56/66
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
CS
CLK
DI
DO
V SS
ORG
NU
Vcc
Name
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
ROTATED
TSSOP
3
4
5
6
7
8
1
2
Description
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Not Utilized
+1.8V to 5.5V Power Supply
3.1
Chip Select (CS)
Note:
CS must go low between consecutive
A high level selects the device. A low level deselects
the device and forces it into Standby mode. However, a
instructions.
programming cycle which is already initiated and/or in
3.3
Data In (DI)
progress will be completed, regardless of the CS input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
Data In is used to clock in a Start bit, opcode, address
and data synchronously with the CLK input.
programming cycle is completed.
CS must be low for 250 ns minimum (T CSL ) between
3.4
Data Out (DO)
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
Data Out is used in the Read mode to output data syn-
chronously with the CLK input (T PD after the positive
edge of CLK).
3.2
Serial Clock (CLK)
This pin also provides Ready/Busy status information
The serial clock is used to synchronize the communica-
tion between a master device and the 93LC46/56/66.
Opcode, address and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T CKH ) and
clock low time (T CKL ). This gives the controlling master
during erase and write cycles. Ready/Busy status infor-
mation is available on the DO pin if CS is brought high
after being low for minimum chip select low time (T CSL )
and an erase or write operation has been initiated.
The Status signal is not available on DO, if CS is held
low or high during the entire write or erase cycle. In all
other cases DO is in the High-Z mode. If status is
checked after the write/erase cycle, a pull-up resistor
on DO is required to read the Ready signal.
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
3.5
Organization (ORG)
CS is high, but Start condition has not been detected,
any number of clock cycles can be received by the
device without changing its status (i.e., waiting for Start
condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are required
to clock in all required opcode, address and data bits
before an instruction is executed (see instruction set
truth table). CLK and DI then become “don't care” inputs
waiting for a new Start condition to be detected.
DS21712B-page 10
When ORG is connected to V CC , the (x16) memory
organization is selected. When ORG is tied to V SS , the
(x8) memory organization is selected. ORG can only be
floated for clock speeds of 1 MHz or less for the (x16)
memory organization. For clock speeds greater than
1 MHz, ORG must be tied to V CC or V SS .
? 2004 Microchip Technology Inc.
相关PDF资料 |
PDF描述 |
|---|---|
| 93LC86C-I/MS | IC EEPROM 16KBIT 3MHZ 8MSOP |
| 93AA86C-I/MS | IC EEPROM 16KBIT 3MHZ 8MSOP |
| 93AA46/SN | IC EEPROM 1KBIT 2MHZ 8SOIC |
| 25LC040A-I/ST | IC EEPROM 4KBIT 10MHZ 8TSSOP |
| 93AA86C-I/ST | IC EEPROM 16KBIT 3MHZ 8TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 93LC46-SL | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-SM | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46SN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 2.5V Microwire Serial EEPROM |
| 93LC46-SN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46T | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 2.5V Microwire Serial EEPROM |
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