参数资料
型号: 93LC46/P
厂商: Microchip Technology
文件页数: 6/20页
文件大小: 0K
描述: IC EEPROM 1KBIT 1MHZ 8DIP
标准包装: 60
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1K(128 x 8 或 64 x 16)
速度: 1MHz
接口: Microwire 3 线串行
电源电压: 2.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
产品目录页面: 1450 (CN2011-ZH PDF)
93LC46/56/66
2.0
FUNCTIONAL DESCRIPTION
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
When the ORG pin is connected to V CC , the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instruc-
performed before any ERASE or WRITE instruction can
be executed.
tions, addresses and write data are clocked into the
DI pin on the rising edge of the clock (CLK). The DO
2.4
Read
pin is normally held in a high-Z state except when
reading data from the device, or when checking the
Ready/Busy status during a programming operation.
The Ready/Busy status can be verified during an
erase/write operation by polling the DO pin; DO low
indicates that programming is still in progress, while
DO high indicates the device is ready. The DO will
enter the high-Z state on the falling edge of the CS.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T PD ). Sequential read is
possible when CS is held high. The memory data will
automatically cycle to the next register and output
sequentially.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
2.5
Erase/Write Enable and Disable
( EWEN , EWDS )
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device opera-
tion (Read, Write, Erase, EWEN, EWDS, ERAL and
WRAL). As soon as CS is high, the device is no longer
in the Standby mode.
An instruction following a Start condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
The 93LC46/56/66 power up in the Erase/Write Disable
(EWDS) state. All programming modes must be
preceded by an Erase/Write Enable ( EWEN ) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V CC is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all erase/write functions and should
follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS
instructions.
the last required address or data bit) CLK and DI
become “don't care” bits until a new Start condition is
2.6
Erase
detected.
The ERASE instruction forces all data bits of the speci-
fied address to the logical “ 1 ” state. CS is brought low
2.2
Data In/Data Out (DI/DO)
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T CSL ). DO at logical “ 0 ” indicates that program-
ming is still in progress. DO at logical “ 1 ” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The erase cycle takes 4 ms per word typical.
2.3
Data Protection
During power-up, all programming modes of operation
are inhibited until V CC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V CC has fallen below 1.4V at nominal conditions.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
DS21712B-page 6
? 2004 Microchip Technology Inc.
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