- 您现在的位置：买卖IC网 > PDF目录122717 > 954201BFLFT (INTEGRATED DEVICE TECHNOLOGY INC) 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 PDF资料下载
参数资料
| 型号： | 954201BFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56 |
| 文件页数： | 12/20页 |
| 文件大小： | 219K |
| 代理商： | 954201BFLFT |
2
Integrated
Circuit
Systems, Inc.
ICS954201
0819H—02/17/06
Pin Description
PIN # PIN NAME
PIN
TYPE
DESCRIPTION
1
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
2
GND
PWR
Ground pin.
3
PCICLK3
OUT
PCI clock output.
4
PCICLK4
OUT
PCI clock output.
5
PCICLK5
OUT
PCI clock output.
6
GND
PWR
Ground pin.
7
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
8
ITP_EN/PCICLK_F0
I/O
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
9
PCICLK_F1
OUT
Free running PCI clock not affected by PCI_STOP# .
10
Vtt_PwrGd#/PD
IN
Vtt_PwrGd# is an active low input used to determine when
latched inputs are ready to be sampled. PD is an asynchronous
active high input pin used to put the device into a low power
state. The internal clocks, PLLs and the crystal oscillator are
stopped.
11
VDD48
PWR
Power pin for the 48MHz output.3.3V
12
USB_48MHz/FS_A
I/O
Frequency select latch input pin / Fixed 48MHz USB clock
output. 3.3V.
13
GND
PWR
Ground pin.
14
DOTT_96MHz
OUT
True clock of differential pair for 96.00MHz DOT clock.
15
DOTC_96MHz
OUT
Complement clock of differential pair for 96.00MHz DOT clock.
16
FS_B/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and
REF/N divider mode while in test mode. Refer to Test
Clarification Table.
17
SRCCLKT0
OUT
True clock of differential SRC clock pair.
18
SRCCLKC0
OUT
Complement clock of differential SRC clock pair.
19
SRCCLKT1
OUT
True clock of differential SRC clock pair.
20
SRCCLKC1
OUT
Complement clock of differential SRC clock pair.
21
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
22
SRCCLKT2
OUT
True clock of differential SRC clock pair.
23
SRCCLKC2
OUT
Complement clock of differential SRC clock pair.
24
SRCCLKT3
OUT
True clock of differential SRC clock pair.
25
SRCCLKC3
OUT
Complement clock of differential SRC clock pair.
26
SRCCLKT4_SATA
OUT
True clock of differential SRC/SATA pair.
27
SRCCLKC4_SATA
OUT
Complement clock of differential SRC/SATA pair.
28
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
相关PDF资料 |
PDF描述 |
|---|---|
| 935271490512 | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 935271979118 | 8 I/O, PIA-GENERAL PURPOSE, PQCC16 |
| 935263358512 | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 9UMS9633BKLFT | 166.67 MHz, OTHER CLOCK GENERATOR, PQCC48 |
| 935263686518 | 6 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 954201BGLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 954201BGLFT | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 954201BGLN | 制造商:Integrated Device Technology Inc 功能描述:PROGRAMMABLE PLL CLOCK SYNTHESIZER DUAL 56TSSOP - Rail/Tube |
| 954201BGLNT | 制造商:Integrated Device Technology Inc 功能描述:954201BGLNT - Tape and Reel |
| 954204BGLF | 制造商:Integrated Device Technology Inc 功能描述:56 TSSOP (LEAD FREE) - Rail/Tube |
发布紧急采购，3分钟左右您将得到回复。