参数资料
型号: 954201BFLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56
文件页数: 3/20页
文件大小: 219K
代理商: 954201BFLFT
11
Integrated
Circuit
Systems, Inc.
ICS954201
0819H—02/17/06
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
CPUCLK2_ITP/SRCCLK7 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 6
SRCCLK6 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 5
SRCCLK5 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 4
SRCCLK4 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 3
SRCCLK3 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 2
SRCCLK2 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 1
SRCCLK1 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 0
SRCCLK0 Enable
Output Enable
RW
DISABLE
ENABLE
1
SMBus Table: Spreading and Device Behavior Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PCI_F0 Enable
Output Enable
RW
Disable
Enable
1
Bit 6
DOT_96MHz Enable
Output Enable
RW
Disable
Enable
1
Bit 5
USB_48MHz Enable
Output Enable
RW
Disable
Enable
1
Bit 4
REFOUT Enable
Output Enable
RW
Disable
Enable
1
Bit 3
1
Bit 2
CPUCLK1
Output Enable
RW
Disable
Enable
1
Bit 1
CPUCLK0
Output Enable
RW
Disable
Enable
1
Bit 0
Spread Spectrum Mode
Spread Off
RW
SPREAD OFF
SPREAD
ON
0
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PCICLK5
Output Enable
RW
Disable
Enable
1
Bit 6
PCICLK4
Output Enable
RW
Disable
Enable
1
Bit 5
PCICLK3
Output Enable
RW
Disable
Enable
1
Bit 4
PCICLK2
Output Enable
RW
Disable
Enable
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
PCI_F1 Enable
Output Enable
RW
Disable
Enable
1
RESERVED
Byte 2
Byte 0
-
RESERVED
-
Byte 1
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